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A case for routing cache on HPC switches

Shin-ichi Ishida, Michihiro Koibuchi, Hiroaki Nishi
2012 IEICE Communications Express  
Our simulation results show that the only 256-entry routing cache hits 98% on over 4k-host systems with the matrix-transpose traffic, and the 1024-entry routing cache improves not only up to 16% of packet  ...  latency but also up to 18% of network throughput.  ...  The fully associative caches outperform 1-and 4-way set associative caches, and the latency and throughput of 1-and 4-way set associative caches are close to those of the case for no caches.  ... 
doi:10.1587/comex.1.49 fatcat:fb6ynmbltvgfxbtxfanyrruuay

An adaptive serial-parallel CAM architecture for low-power cache blocks

Aristides Efthymiou, Jim D. Garside
2002 Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02  
There is an on-going debate about which consumes less energy: a RAM-tagged associative cache with an intelligent order of accessing its tags and ways (e.g. way prediction), or a CAM-tagged high associativity  ...  cache.  ...  Efthymiou is funded by the Department of Computer Science, University of Manchester. This support is gratefully appreciated.  ... 
doi:10.1145/566443.566445 fatcat:b74d6orjbfbqphltcghghuetnm

An adaptive serial-parallel CAM architecture for low-power cache blocks

Aristides Efthymiou, Jim D. Garside
2002 Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02  
There is an on-going debate about which consumes less energy: a RAM-tagged associative cache with an intelligent order of accessing its tags and ways (e.g. way prediction), or a CAM-tagged high associativity  ...  cache.  ...  Efthymiou is funded by the Department of Computer Science, University of Manchester. This support is gratefully appreciated.  ... 
doi:10.1145/566408.566445 dblp:conf/islped/EfthymiouG02 fatcat:z7vify37efbvbchzmpea2saudy

An adaptive serial-parallel CAM architecture for low-power cache blocks

A. Efthymiou, J.D. Garside
2002 Proceedings of the International Symposium on Low Power Electronics and Design  
There is an on-going debate about which consumes less energy: a RAM-tagged associative cache with an intelligent order of accessing its tags and ways (e.g. way prediction), or a CAM-tagged high associativity  ...  cache.  ...  Efthymiou is funded by the Department of Computer Science, University of Manchester. This support is gratefully appreciated.  ... 
doi:10.1109/lpe.2002.146726 fatcat:53mkjvgjxzbr7i74ml2gn2pumu

Selective block buffering TLB system for embedded processors

J.-H. Lee, C. Weems, S.-D. Kim
2005 IEE Proceedings - Computers and digital Techniques  
Dynamic power is reduced by , 93% with respect to a fully associative TLB, 87% with respect to a filter-TLB and 60% relative to a banked-TLB with block buffering.  ...  Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism.  ...  Cache access latency is greater on a miss in the filter cache, but line buffering [6, 11, 12] reduces latency by accessing a 4-entry fully associative cache in parallel with the normal cache.  ... 
doi:10.1049/ip-cdt:20045025 fatcat:2l4ukb6tjbgklmjdh2zu6ibgz4

Evaluating Novel Memory System Alternatives for Speculative Multithreaded Computer Systems [chapter]

A. J. KleinOsowski, David J. Lilja
2004 High Performance Memory Systems  
Multithreaded architectures which support the speculative execution of multiple concurrent threads of execution require a special speculative memory buffer to detect and potentially correct dependences  ...  As a related question, we also evaluate whether the traditional cache structure should be private to each processing element, or whether the cache should be shared among all processing elements.  ...  Acknowledgments [12] of this work.  ... 
doi:10.1007/978-1-4419-8987-1_16 fatcat:z4uk3labgbdbrhoxk3t3h75ngq

Randomized cache placement for eliminating conflicts

N. Topham, A. Gonzalez
1999 IEEE transactions on computers  
Our conclusions are supported by simulations of a superscalar out-of-order processor executing the SPEC95 benchmarks, as well as from cache simulations of individual loop kernels to illustrate specific  ...  The tension between minimizing cache conflicts and the other transformations needed for efficient parallelization leads to complex optimization problems for parallelizing compilers.  ...  In the case of hydro2d and apsi, some organizations exhibit lower miss ratios than a fully-associative cache due to suboptimality of LRU replacement in a fully-associative cache for these particular programs  ... 
doi:10.1109/12.752660 fatcat:ymq6sj4wmjhorlqmvad6leoy6y

Energy Efficient Fully Associative Cache Model

S. Subha
2012 International Journal of Computer Applications  
The proposed model is simulated with SPEC2K benchmarks. The average memory access time is comparable with traditional fully associative cache with energy savings.  ...  This paper proposes an algorithm to map cache line to one block in fully associative cache by XOR'ing the address with constant. Bit selection is applied to the result and the block accessed.  ...  The cache is simulated as an array. Each address is mapped to a block in fully associative cache. The number of hits and misses are gathered from the address trace.  ... 
doi:10.5120/7192-9949 fatcat:mo7rywjvinh5jahr3w52ryfuvm

Phased set associative cache design for reduced power consumption

Rajesh Kannan Megalingam, K.B Deepu, Iype P. Joseph, Vandana Vikram
2009 2009 2nd IEEE International Conference on Computer Science and Information Technology  
The results show an average of 41% reduction in power consumption as compared to the conventional sequential set associative cache and an average of 21% power reduction as compared to conventional parallel  ...  set associative cache architecture.  ...  N way set associative caches are easier to search than fully associative cache.  ... 
doi:10.1109/iccsit.2009.5234663 fatcat:o4s4wzuk7baozawbp2ekuke7bu

Simulation of direct mapped, k-way and fully associative cache on all pairs shortest paths algorithms

A. A. Prihozhy
2019 Sistemnyj Analiz i Prikladnaâ Informatika  
This paper presents a technique of simulating the direct mapped, k-way associative and fully associative cache during the algorithm execution, to measure the frequency of read data to cache and write data  ...  The hit and miss rate depends on the cache type: direct mapped, set associative and fully associative cache. The least recently used replacement policy serves the sets.  ...  of fully associative cache For fully associative cache, we simulate the replacement strategy LRU that serves all cache slots.  ... 
doi:10.21122/2309-4923-2019-4-10-18 fatcat:6lflxb3k7ffevnedvwtcul7y2i

Hardware and software cache prefetching techniques for MPEG benchmarks

D.F. Zucker, R.B. Lee, M.J. Flynn
2000 IEEE transactions on circuits and systems for video technology (Print)  
The stream cache can cut execution time by more than half with the addition of a relatively small amount of additional hardware.  ...  As processors get faster-both in terms of higher clock speeds and increased instruction level parallelism-the time spent in the memory system becomes even more significant.  ...  The series-stream cache is queried after a main cache miss, and is used to fill the main cache with the main cache. The series-stream cache simulated is fully associative.  ... 
doi:10.1109/76.856455 fatcat:l6fwj35nefeyzbgg5efiztwdie

Reducing the associativity and size of step caches in CRCW operation

M. Forsell
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
According to the evaluation, the performance of limited associativity step cache systems comes very close to that of fully associative step cache systems, while decreasing the size of caches decreases  ...  We give a short performance evaluation of limited associativity step cache systems with different settings using simple parallel programs on a parametrical MP-SOC framework.  ...  Acknowledgements This work was supported by the grant 107177 of the Academy of Finland.  ... 
doi:10.1109/ipdps.2006.1639546 dblp:conf/ipps/Forsell06 fatcat:p6dnlsiw5jddlfuk2iydpd52gm

Design of Trace-Based Split Array Caches for Embedded Applications

Alice M. Tokarnia, Marina Tachibana
2010 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools  
of the unified set-associative array cache with the lowest energy-delay product.  ...  For an MPEG-2 decoder, even with no parallel accesses to cache partitions, the average memory access energy-delay product of an 8K-byte trace-based split array cache is reduced by 50% as compared to that  ...  Thanks also to the professors and the students of the Computer Engineering and Industrial Automation Laboratory that postponed their work so that the cache simulations could run on several machines.  ... 
doi:10.1109/dsd.2010.33 dblp:conf/dsd/TokarniaT10 fatcat:aa6davqysvh7rg2byj6hldom6e

A media cache structure for multimedia applications in embedded systems

Jung-hoon Lee
2011 IEICE Electronics Express  
The proposed cache consists of three parts, i.e., a dual direct mapped cache, a fully associative spatial buffer, and a dynamic fetch unit.  ...  Simulation results show that the proposed cache can achieve better performance than a 2-way or 4-way set associative cache with twice as much space.  ...  When the CPU performs a memory reference, both the fully associative cache and one of the two direct mapped caches are searched in parallel within one cycle.  ... 
doi:10.1587/elex.8.1302 fatcat:tzogvhrq3ffivjpsy5oix3sfpu

An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications

J.-H. Lee, G.-H. Park, Shin-Dug Kim
2003 Eleventh Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2003. Proceedings.  
In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with four or twice as much space respectively.  ...  Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space.  ...  Acknowledgments This research was supported by System LSI Business of Samsung Electronics Co., Ltd. Korea.  ... 
doi:10.1109/empdp.2003.1183574 dblp:conf/pdp/LeePK03 fatcat:7astuc2umrh3xjpz6robaqfbpu
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