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Parallel RAM algorithms for factorizing words

J.W. Daykin, C.S. Iliopoulos, W.F. Smyth
1994 Theoretical Computer Science  
An O(logn loglogn) CRCW PRAM algorithm using O(n/logn) processors for computing the unique Lyndon factorization of a word of length n over an unbounded alphabet is presented; this improves the bounds given  ...  Moreover, in the case of fixed alphabets the CRCW PRAM algorithm is optimal (linear cost), requiring O(log n) units of time.  ...  Duval considered the sequential computation of the CFL decomposition, and here we present a parallel algorithm for this important factorization.  ... 
doi:10.1016/0304-3975(94)90100-7 fatcat:7g75xz75xfeiblqk7mtqylv3by

Algorithms in the Ultra-Wide Word Model [article]

Arash Farzan, Alejandro López-Ortiz, Patrick K. Nicholson, Alejandro Salinger
2014 arXiv   pre-print
For the standard word-RAM algorithms, the speedups obtained are moderate, as they are limited by the word size.  ...  We introduce the Ultra-Wide Word architecture and model, an extension of the word-RAM model that allows for constant time operations on thousands of bits in parallel.  ...  of word-ram algorithms through operations on thousands of bits in parallel.  ... 
arXiv:1411.7359v2 fatcat:clbzeuu6fnftxmypyw7xuxaxly

A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems

J. LEE, H. LEE
2008 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-2 4 FFT/IFFT processor for MB-OFDM ultrawideband (UWB) systems.  ...  The radix-2 4 FFT algorithm is also realized in our processor to reduce the number of complex multiplications.  ...  First, for the two-parallel data path operation, the two of the complex inputs are stored in the RAM.  ... 
doi:10.1093/ietfec/e91-a.4.1206 fatcat:puwxmoz44bbuvk33a6owm7vgq4

Algorithms in the Ultra-Wide Word Model [chapter]

Arash Farzan, Alejandro López-Ortiz, Patrick K. Nicholson, Alejandro Salinger
2015 Lecture Notes in Computer Science  
We introduce the Ultra-Wide Word architecture and model, an extension of the word-RAM model, that allows for constant time operations on thousands of bits in parallel.  ...  In practice, the speedups obtained by word-RAM algorithms are moderate, as they are limited by the word size.  ...  of word-RAM algorithms through operations on thousands of bits in parallel.  ... 
doi:10.1007/978-3-319-17142-5_29 fatcat:2aq3no5dd5hybehol74c2mh2ve

Towards optimal packed string matching

Oren Ben-Kiki, Philip Bille, Dany Breslauer, Leszek Ga̧sieniec, Roberto Grossi, Oren Weimann
2014 Theoretical Computer Science  
We propose micro-level algorithms for the theoretically efficient emulation using parallel algorithms techniques to emulate wssm and using the Four-Russians technique to emulate wslm.  ...  Our macro-level algorithm only uses the standard AC 0 instructions of the word-RAM model (i.e. no integer multiplication) plus two specialized micro-level AC 0 word-size packed-string instructions.  ...  Acknowledgments We are grateful to Simone Faro and Thierry Lecroq for making their SMART framework available.  ... 
doi:10.1016/j.tcs.2013.06.013 fatcat:rmogaz5pqfhdvmzt5wooto6loa

A high performance four-parallel 128/64-point radix-24 FFT/IFFT processor for MIMO-OFDM systems

Hang Liu, Hanho Lee
2008 APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems  
This paper presents a design and implementation result of a high-speed, low-complexity four data-path 64point radix-2 4 FFT/IFFT processor for high-throughput MIMO-OFDM wireless LAN system.  ...  The proposed FFT/IFFT processor can provide a higher throughput rate and low hardware complexity by using a four-parallel datapath scheme and a multipath delay feed-back (MDF) structure.  ...  For the four-parallel approach to implement the radix-2 4 FFT algorithm, we design the four-parallel data path complex Booth multipliers module.  ... 
doi:10.1109/apccas.2008.4746152 dblp:conf/apccas/LiuL08 fatcat:5gxogoobrrdpfbpj2v6phxggmq

Oblivious Network RAM and Leveraging Parallelism to Achieve Obliviousness [chapter]

Dana Dachman-Soled, Chang Liu, Charalampos Papamanthou, Elaine Shi, Uzi Vishkin
2015 Lecture Notes in Computer Science  
We present new constructions for obliviously simulating general or parallel programs in the Network RAM model.  ...  In other words, obliviousness within each bank comes for free-either because the architecture prevents a malicious party from observing the address accessed within a bank, or because another solution is  ...  Lemma 2 (Log * -time parallel algorithm for colored compaction [4] ).  ... 
doi:10.1007/978-3-662-48797-6_15 fatcat:zxmytox75rfzrkobd5errdzzne

Oblivious Network RAM and Leveraging Parallelism to Achieve Obliviousness

Dana Dachman-Soled, Chang Liu, Charalampos Papamanthou, Elaine Shi, Uzi Vishkin
2018 Journal of Cryptology  
Oblivious RAM (ORAM) is a cryptographic primitive that allows a trusted CPU to securely access untrusted memory, such that the access patterns reveal nothing about sensitive data.  ...  ORAM is known to have broad applications in secure processor design and secure multi-party computation for big data.  ...  In the process, we propose novel algorithmic techniques that "leverage parallelism for obliviousness".  ... 
doi:10.1007/s00145-018-9301-4 fatcat:4uu32x765jhafnvyvibflmbgbq

Pipelined Decomposable BSP Computers [chapter]

Martin Beran
2001 Lecture Notes in Computer Science  
The class of weak parallel machines is interesting, because it contains some realistic parallel machine models, especially suitable for pipelined computations.  ...  For example, in a single step of a parallel Turing machine, information can be transferred from a tape cell to its immediate neighbours only.  ...  pipelined computer, an interactive machine processes a (potentially infinitely) long sequence of input data, produces corresponding output data, and is able to store information in its internal memory for  ... 
doi:10.1007/3-540-45627-9_14 fatcat:nmwwpzyqgbc77ffdllm7osy5wa

Multiple serial episode matching [article]

Patrick Cegielski, Yuri Matiyasevich
2006 arXiv   pre-print
O(n) on-line algorithm for solving the serial episode matching problem on MP--RAMs when there is only one single episode.  ...  In a previous paper we generalized the Knuth-Morris-Pratt (KMP) pattern matching algorithm and defined a non-conventional kind of RAM, the MP--RAMs (RAMS equipped with extra operations), and designed an  ...  The word p = p 1 p 2 · · · p k is a factor of t iff, there exists an integer j such that t j+i = p i for 1 ≤ i ≤ k.  ... 
arXiv:cs/0603050v1 fatcat:fzttwmravjbahdexptuk4ejmru

Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders

Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
2011 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Index Terms-Alignment, field programmable logic array (FPGA), folding, low-density parity-check (LDPC) decoder, memory system optimization, normalized min-sum algorithm, quasi-cyclic low-density parity-check  ...  paper presents two specific optimizations called vectorization and folding to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for  ...  There are IMEMs for a -regular QC-LDPC codes. Every message is stored in one memory word of the block RAM.  ... 
doi:10.1109/tcsi.2010.2055250 fatcat:2zc7gaotrrdlhl37ul52mp3bhi

Multiple serial episodes matching

Patrick Cégielski, Irène Guessarian, Yuri Matiyasevich
2006 Information Processing Letters  
designed an O(n) on-line algorithm for solving the serial episode matching problem on MP-RAMs when there is only one single episode.  ...  In [BCGM01] we have generalized the Knuth-Morris-Pratt (KMP) pattern matching algorithm and defined a nonconventional kind of RAM, the MP-RAMs which model more closely the microprocessor operations, and  ...  The word p = p 1 p 2 · · · p k is a factor of t iff, there exists an integer j such that t j+i = p i for 1 ≤ i ≤ k.  ... 
doi:10.1016/j.ipl.2006.02.008 fatcat:wtyj3jylq5bpxbwyqvdd5peoli

Pipelined Decomposable BSP Computers

Martin Beran
2002 RAIRO - Theoretical Informatics and Applications  
The class of weak parallel machines is interesting, because it contains some realistic parallel machine models, especially suitable for pipelined computations.  ...  For example, in a single step of a parallel Turing machine, information can be transferred from a tape cell to its immediate neighbours only.  ...  pipelined computer, an interactive machine processes a (potentially infinitely) long sequence of input data, produces corresponding output data, and is able to store information in its internal memory for  ... 
doi:10.1051/ita:2002004 fatcat:rpyrlcdhnzg2zgtyp5dw5x4kl4

Architecture and finite precision optimization for layered LDPC decoders

Cedric Marchand, Laura Conde-Canencia, Emmanuel Boutillon
2010 2010 IEEE Workshop On Signal Processing Systems  
The finite precision model determines the area of the decoder, which is mainly composed of memory, especially for long frames.  ...  In this figure, the NP block is made of 45 NP (Fig. 10) working in parallel. The Barrel Shifter shifts seven words of size 45. The RAM SO block stores the SO values.  ...  Fig. 9 shows the total memory capacity as a function of the word length W RAM . There are local minimum for word sizes 1, 9, 14, 18 and 21 bits.  ... 
doi:10.1109/sips.2010.5624816 fatcat:a5xozqskwncttni4oiz3q2obci

Page 3203 of Mathematical Reviews Vol. , Issue 98E [page]

1998 Mathematical Reviews  
This paper gives an improved algorithm for detecting morphic images of a word, improving on the author's previous work.  ...  For the entire collection see MR 98c:68009. } 98e:68112 68Q25 68R15 Néraud, Jean (F-ROUENS-LI; Mont-Saint-Aignan) Detecting the morphic images of a word: improving the general algorithm.  ... 
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