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Parallel Prefix Adder Design with Matrix Representation
17th IEEE Symposium on Computer Arithmetic (ARITH'05)
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This paper presents a one-shot batch process that generates a wide range of designs for a group of parallel prefix adders. ...
The prefix adders are represented by two two-dimensional matrixes and two vectors. ...
In summary, the proposed matrix representation of the Knowles adders is a mathematical representation of a gate level design of the adders. ...
doi:10.1109/arith.2005.35
dblp:conf/arith/ChoiS05
fatcat:p2a42g6m75fjxe6afqomhhac2m
Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA
2012
International Journal of Computer Applications
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Parallel prefix adder is the most flexible and widely used for binary addition. Parallel Prefix adders are best suited for VLSI implementation. ...
These operators are designed using multiplexers. The proposed hybrid architecture is implemented with 16-bit width operands on Xilinx Spartan 3E FPGA. ...
A fast characterization process for Knowles adders is proposed using matrix representation [10] . In [13] , a hybrid architecture is proposed with different operators. ...
doi:10.5120/9246-3410
fatcat:gw6foqr6xfh3xfao655zeu5kii
Design of efficient modulo 2n+1 multipliers
2007
IET Computers & Digital Techniques
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It is also proposed that part of the correction factor is treated as a partial product, whereas the rest is handled by the final parallel adder. ...
A new modulo 2 n þ 1 multiplier architecture is proposed for operands in the weighted representation. ...
As a result, parallel-prefix adder architectures with log 2 n have been derived, that is inverted EAC adders that can achieve the same operating speed as the corresponding integer adders. ...
doi:10.1049/iet-cdt:20060026
fatcat:wgemk3p3mneqfp2hkr27rg3sfi
Novel Modulo 2^n + 1 Multipliers
2006
9th EUROMICRO Conference on Digital System Design (DSD'06)
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The proposed architecture utilizes a total of (n + 1) partial products, each n bits wide and is built using an inverted end-around-carry, carry-save adder tree and a final parallel adder. * ...
adder. ...
The delay of the parallel-prefix inverted EAC adder is [7] : T adder = 2 log 2 n + 3. ...
doi:10.1109/dsd.2006.71
dblp:conf/dsd/VergosE06
fatcat:wnhpbyza3nhstn3wwd3vkm3yge
Optimistic Parallelization of Floating-Point Accumulation
2007
Computer Arithmetic
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On this 16 PE design, we demonstrate an average speedup of 6× with randomly generated data and 3-7× with summations extracted from Conjugate Gradient benchmarks. ...
We map this computation to a network of 16 statically-scheduled, pipelined, double-precision floating-point adders on the Virtex-4 LX160 (-12) device where each floating-point adder runs at 296 MHz and ...
We expect there is room to improve upon these results by more carefully exploring the parallel-prefix design space. VII. ...
doi:10.1109/arith.2007.25
dblp:conf/arith/KapreD07
fatcat:3nx746ttpbhazkyoa4jpemrqre
PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning
[article]
2022
arXiv
pre-print
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2021
2021 58th ACM/IEEE Design Automation Conference (DAC)
unpublished
doi:10.1109/dac18074.2021.9586094 fatcat:lvvgqaymgzc53bowluy5ixjngm
doi:10.1109/dac18074.2021.9586094 fatcat:lvvgqaymgzc53bowluy5ixjngm
In this work, we present a reinforcement learning (RL) based approach to designing parallel prefix circuits such as adders or priority encoders that are fundamental to high-performance digital design. ...
We design a grid-based state-action representation and an RL environment for constructing legal prefix circuits. ...
as (parallel) prefix circuits [1] . ...
arXiv:2205.07000v1
fatcat:r2eg2qrzonglta6a5kmkwobady
Implementation of Error Detection Network in High- Speed Variable Latency Speculative Han-Carlson Adder
2016
International Journal of Science and Research (IJSR)
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This paper proposes a novel variable latency speculative adder based on Han-Carlson parallel-prefix topology which proposes the error detection network that reduces error probability compared to previous ...
Variable latency adders have been recently proposed in literature. In variable latency adder unwanted interconnections also reduced compared with kogge-stone topology. ...
Carlson presented a hybrid construction of a parallel prefix adder using two designs the Kogge-Stone construction having the best feature of higher speed and the Brent-kung construction with best feature ...
doi:10.21275/v5i1.nov152775
fatcat:b6hc22iagjbgvlaqi5d7ptmryi
Reduction and optimal performance of acyclic adders of binary codes
2019
Eastern-European Journal of Enterprise Technologies
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Design of the adders implemented with the use of memristors was presented in [15] where designs based on memristors for standard adder architectures (ripple carry adder, carry lookahead adder and parallel ...
It was also shown that the Kogge-Stone design has better (among the parallel prefix adders) metric in terms of delays and area. ...
in the nanometer range, reappraisal of the adder designs implemented with the use of memristors, etc. ...
doi:10.15587/1729-4061.2019.157150
fatcat:t2co2y3btjcorozzpzeh3vvtdq
Digit-set conversions: generalizations and applications
1994
IEEE transactions on computers
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We generalize known algorithms for conversions into non redundant digit sets, as well as apply conversion to generalize the c)(log 7 1 ) time algorithm for conditional sum addition using parallel prefix ...
Poulton, "Pixel planes: A VLSI oriented design for a raster graphics engine," VLSI Design. ...
ACKNOWLEDGMENT The author acknowledges constructive comments from the referees and fruitful discussions with D. Matula conceming the proof of Theorem 2.1 and his notation from [6] as used here. ...
doi:10.1109/12.280811
fatcat:4qq752pswzd7dg4az2ahcrp22m
Extending Sparse Tensor Accelerators to Support Multiple Compression Formats
[article]
2021
arXiv
pre-print
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Support for this work was provided through the ARIAA co-design center funded by the U.S. Department of Energy (DOE) Office of Science, Advanced Scientific Computing Research program. ...
To reduce MINT mr's area and power overhead, a serial chain prefix sum design (Fig. 9a) can be used instead of a highly parallel prefix sum design (Fig. 9c) . ...
We enable highly parallel prefix sum of 32 inputs by modifying adders with forwarding links and muxes. The size of 32 is selected to satisfy MINT throughput requirement. ...
arXiv:2103.10452v1
fatcat:jsn7psgnhra4zngrwt7hhgdzs4
Implementation of Orthogonal Frequency Division Multiplexing Modem Using Radix-N Pipeline Fast Fourier Transform (FFT) Processor
2003
Japanese Journal of Applied Physics
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The newly proposed scheme has a simple control structure and multiplication block is designed based on canonic signed digit (CSD) with N=4 twiddle factors, which enables both hardware complexity and power ...
In order to verify the real time operation, the IEEE802.11a baseband OFDM test-bed with the newly proposed Radix-N pipeline FFT processor is implemented using field programmable gate array (FPGA) devices ...
In case of parallel multiplier, W[bit] Â W[bit] multiplication based on the 2's complement representation needs at least ðW À 1Þ 2 of full adders. ...
doi:10.1143/jjap.42.2176
fatcat:wvokoy4bujcrfnngixbjgjwd2m
High-Performance, Cost-Effective 3D Stacked Wide-Operand Adders
2017
IEEE Transactions on Emerging Topics in Computing
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An N-bit adder implemented on a K identical tier stacked IC performs in parallel two N=K-bit additions on each tier according to the anticipated computation principle. ...
Different from state of the art direct folding proposals we introduce two cost-effective 3D Stacked Hybrid Adders with identical tier structure, which potentially makes the manufacturing of hardware wide-operand ...
PARALLEL PREFIX ADDERS (PPA) 3D PARTITIONING The straightforward way to design a 3D stacked fast adder is to take an existing planar prefix adder, partition it, and fold the resulting partitions such that ...
doi:10.1109/tetc.2016.2598290
fatcat:gjyadya5ineltfwruojyrq6fue
Parallel progressive multiple sequence alignment on reconfigurable meshes
2011
BMC Genomics
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To align m sequences with max length n, we combining the parallel pair-wise dynamic programming solutions with newly designed parallel components. ...
We also provide a new parallel algorithm for the Longest Common Subsequence (LCS) with O(1) run-time using O(n 3 ) processing units. ...
Using scaled-up scoring matrices will eliminate the need for signed number representation in our following algorithm designs. ...
doi:10.1186/1471-2164-12-s5-s4
pmid:22369070
pmcid:PMC3287500
fatcat:rdlryu4xjje63iuhxycg56yvnq
Synthesis of parallel adders from if-decision diagrams
2020
Sistemnyj Analiz i Prikladnaâ Informatika
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If-decision diagrams provide a parallel many-bit adder model with the time complexity of Ο(log2n) and area complexity of Ο(n×log2n). ...
We propose a blocked structure of the parallel if-diagram-based adders, and introduce an adder table representation, which is capable of systematic producing if-diagram of any bit-width. ...
Kogge-Stone adder (KSA) is a parallel prefix carry look-ahead adder [3] . ...
doi:10.21122/2309-4923-2020-2-61-70
fatcat:c5apneo23zc3dbi3uwaw7x5qsm
Compiling Low Depth Circuits for Practical Secure Computation
[chapter]
2016
Lecture Notes in Computer Science
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For an exemplary biometric matching application we report a 400× speed-up in comparison with a circuit generated from a size-minimizing compiler. ...
With the rise of practical Secure Multi-party Computation (MPC) protocols, compilers have been developed that create Boolean or Arithmetic circuits for MPC from functionality descriptions in a highlevel ...
A Parallel Prefix Adders for MPC A PPA uses a parallel prefix circuit, cf. § 3, over two inputs, named the generate G i:j and the propagate P i:j signal. ...
doi:10.1007/978-3-319-45741-3_5
fatcat:jp4ltdj7vfeo3e3m5mwhdjufrq
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