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Parallel Logic Simulation of VLSI Systems

Roger D. Chamberlain
<span title="">1995</span> <i title="ACM"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/bonikunskbdgjicnz3tvcz7334" style="color: black;">Proceedings - Design Automation Conference</a> </i> &nbsp;
As a result, researchers are attempting to exploit parallel processing techniques to improve the performance of VLSI logic simulation.  ...  This tutorial describes the current state-of-the-art in parallel logic simulation, including parallel simulation techniques, factors that impact simulation performance, performance results to date, and  ...  ACKNOWLEDGMENT The author would like to thank Mary Bailey for her insightful comments on an early draft of this manuscript.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dac.1995.250078">doi:10.1109/dac.1995.250078</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6z2noirad5gllocr7vab4yokqu">fatcat:6z2noirad5gllocr7vab4yokqu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20060828111439/http://www.ccrc.wustl.edu/~roger/papers/chamberlain95.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/36/0c/360c6adfdf92d312780fca786a749f03f6dc0f38.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dac.1995.250078"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Parallel logic simulation of VLSI systems

Mary L. Bailey, Jack V. Briner, Roger D. Chamberlain
<span title="1994-09-01">1994</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/eiea26iqqjcatatlgxdpzt637y" style="color: black;">ACM Computing Surveys</a> </i> &nbsp;
Fast, efficient logic simulators are an essential tool in modern VLSI system design.  ...  The circuit structure of the VLSI system, as well as its input vectors, can have a dramatic effect on the performance of parallel simulations.  ...  Obviously, obtaining good performance from parallel logic simulation is nontrivial.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/185403.185424">doi:10.1145/185403.185424</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/zvoo2ptninbmvlcehkod5wthfq">fatcat:zvoo2ptninbmvlcehkod5wthfq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170811042041/http://www.ccrc.wustl.edu/~roger/569M.s09/p255-bailey.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a1/ae/a1ae8e4565813da70c8cc53d71a50ae2a79c88f9.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/185403.185424"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Parallel logic simulation of VLSI systems

Roger D. Chamberlain
<span title="">1995</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5vn6yyeefbbxtoo3uhwxwjwtme" style="color: black;">Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC &#39;95</a> </i> &nbsp;
As a result, researchers are attempting to exploit parallel processing techniques to improve the performance of VLSI logic simulation.  ...  This tutorial describes the current state-of-the-art in parallel logic simulation, including parallel simulation techniques, factors that impact simulation performance, performance results to date, and  ...  ACKNOWLEDGMENT The author would like to thank Mary Bailey for her insightful comments on an early draft of this manuscript.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/217474.217520">doi:10.1145/217474.217520</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dac/Chamberlain95.html">dblp:conf/dac/Chamberlain95</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/r7pbllgnnzaytedlvbd6blno4m">fatcat:r7pbllgnnzaytedlvbd6blno4m</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20060828111439/http://www.ccrc.wustl.edu/~roger/papers/chamberlain95.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/36/0c/360c6adfdf92d312780fca786a749f03f6dc0f38.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/217474.217520"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Parallel Logic Simulation of Million-Gate VLSI Circuits

Lijuan Zhu, G. Chen, B.K. Szymanski, C. Tropper, Tong Zhang
<i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/z2ot7tezyrgpxlxgssko2bzyw4" style="color: black;">13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems</a> </i> &nbsp;
As a result, gate-level logic simulation has became an integral component of the VLSI circuit design process which verifies the design and analyzes its behavior.  ...  We present the design and implementation of a new parallel simulator, called DSIM, and demonstrate DSIM's efficiency and speed by simulating a million gate circuit using different numbers of processors  ...  Conclusions and future research In this paper, we presented a parallel logic simulator of a million-gate VLSI circuit using a new simulation engine called DSIM.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mascots.2005.48">doi:10.1109/mascots.2005.48</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/mascots/ZhuCSTZ05.html">dblp:conf/mascots/ZhuCSTZ05</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/dtysulxudffqdlnbqbdwhuponu">fatcat:dtysulxudffqdlnbqbdwhuponu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20130328181717/http://www.cs.rpi.edu/~szymansk/papers/mascot.05.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c3/4d/c34d68996d5342f288b8f1ca84c56e5e912fa080.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mascots.2005.48"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

FPGA Realization of Logic Gates using Neural Networks

R. Ganesh, Assoc. Professor, CVR College of Engineering/ECE Department, Hyderabad, India, D. Bhanu Prakash, Assoc. Professor, CVR College of Engineering/ECE Department, Hyderabad, India
<span title="2021-06-01">2021</span> <i title="CVR College of Engineering"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/z3kywlucprfd3kss6fufnbqkva" style="color: black;">CVR Journal of Science &amp; Technology</a> </i> &nbsp;
The real time systems are designed by using analog and digital sub systems with control logic. In the design of digital sub systems the logic gates are the major building blocks.  ...  The Neural Network based logic gates are simulated for different test cases.  ...  Hence, to design Neural Network systems the VLSI is considered as the best method for parallelism [2] . The design approaches for VLSI systems is shown in Figure 1 .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.32377/cvrjst2009">doi:10.32377/cvrjst2009</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/t4a23oz2zbcrtf23ozfp3icr3m">fatcat:t4a23oz2zbcrtf23ozfp3icr3m</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20220209095842/http://cvr.ac.in/ojs/index.php/cvracin/article/download/694/564/" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/62/97/629713718e6d4c2c0ddbaf83916e5ac95e959708.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.32377/cvrjst2009"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Building a Full Scale V LSI-Based Volume Visualization System [chapter]

Reuven Bakalash, Arie Kaufman, Zhong Xu
<span title="">1992</span> <i title="Springer Berlin Heidelberg"> Advances in Computer Graphics Hardware V </i> &nbsp;
The hardware realization of an advanced prototype of the Cube volume visualization system, Cube-3, is presented.  ...  Cube-3 design is based on our experience with two earlier prototypes: Cube-1 realized in hard ware using printed circuit board technology and Cube-2 our first custom-designed VLSI implementation.  ...  Smith for his invaluable advice concerning the VLSI design and testing.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-642-76777-7_9">doi:10.1007/978-3-642-76777-7_9</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/oxqouray7zdubfg6bxbezosjl4">fatcat:oxqouray7zdubfg6bxbezosjl4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170811042441/https://diglib.eg.org/bitstream/handle/10.2312/EGGH.EGGH90.109-115/109-115.pdf?sequence=1" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ea/cc/eacc7183b34d3f3ce9ce1845c7c029001d07e876.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-642-76777-7_9"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Page 15 of Hewlett-Packard Journal Vol. 36, Issue 9 [page]

<span title="">1985</span> <i title="Hewlett-Packard Company"> <a target="_blank" rel="noopener" href="https://archive.org/details/pub_hewlett-packard-journal" style="color: black;">Hewlett-Packard Journal </a> </i> &nbsp;
FTL lends itself to parallel simulation, thereby sav- ing a great deal of time. The custom VLSI CPU gate array tnd » ROMs OUTPUTS Fig. 3.  ...  This process was tedious, but necessary to ensure the accuracy of the system simulation. The next step was to simulate each of the printed circuit assemblies and custom VLSI chips separately.  ... 
<span class="external-identifiers"> </span>
<a target="_blank" rel="noopener" href="https://archive.org/details/sim_hewlett-packard-journal_1985-09_36_9/page/15" title="read fulltext microfilm" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Archive [Microfilm] <div class="menu fulltext-thumbnail"> <img src="https://archive.org/serve/sim_hewlett-packard-journal_1985-09_36_9/__ia_thumb.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a>

D&T Conferences

<span title="">1986</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hkpx3vsnhrfb7jh6hlwads7olq" style="color: black;">IEEE Design &amp; Test of Computers</a> </i> &nbsp;
This is achieved by the application of the learn-mode approach to a logic simulator.  ...  Systems," and "CMU Layout by Annealing in a Parallel Environment."  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mdt.1986.295003">doi:10.1109/mdt.1986.295003</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/q36icdko3rcivdieaaoacmvup4">fatcat:q36icdko3rcivdieaaoacmvup4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190221235002/http://pdfs.semanticscholar.org/35d8/8f699912f7434c6705d07a8cd1f2c8af56d8.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/35/d8/35d88f699912f7434c6705d07a8cd1f2c8af56d8.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mdt.1986.295003"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Design of 4*1 Multiplexer using DPTL based Double Gate MOSFET

G. Parameswara Rao, S. Sai Navya, P. Sireesha, U. Sai Kiran, V. Sravya, T. Narayana Rao
<span title="2019-04-27">2019</span> <i title="Zenodo"> Zenodo </i> &nbsp;
in parallel and it generates dual logic function.  ...  Microwind tool is used for simulation of result.  ...  and Embedded System Volume 4 Issue 1 International Journal of VLSI Design, Microelectronics and Embedded System Volume 4 Issue 1 Symp.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5281/zenodo.2652786">doi:10.5281/zenodo.2652786</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/j6ey6e6iena47matvo7qxjakqq">fatcat:j6ey6e6iena47matvo7qxjakqq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20201225195518/https://zenodo.org/record/2652786/files/Design%20of%2041%20Multiplexer%20using%20DPTL%20based%20%20Double%20Gate%20MOSFET.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a8/f1/a8f1ba76365e6f6bc8c9c09ce65aed1e928723e9.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5281/zenodo.2652786"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> zenodo.org </button> </a>

Simulation of Tree Adder Designed With Complementary Energy Path Adiabatic Logic

B. Nireesha
<span title="">2013</span> <i title="IOSR Journals"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/7ftgkqdzrnfspfyjn3usmdd66q" style="color: black;">IOSR Journal of VLSI and Signal processing</a> </i> &nbsp;
The analyses are carried out using the EDA tool which is the Electric VLSI Design System using 130 nm technology library.  ...  Its performance is also compared against the CAL (Clocked Adiabatic Logic) inverter, which is a dynamic type of adiabatic logic.  ...  Parallel-prefix adders are suitable for VLSI implementation since they rely on the use of simple cells and maintain regular connections between them.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.9790/4200-0342733">doi:10.9790/4200-0342733</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/teldeerkgndv3bainu7crrypfq">fatcat:teldeerkgndv3bainu7crrypfq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180602050731/http://www.iosrjournals.org/iosr-jvlsi/papers/vol3-issue4/D0342733.pdf?id=7679" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/63/87/6387bf84bcb89be898145ce57fd424360c4d596e.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.9790/4200-0342733"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Alternative Architectures Toward Reliable Memristive Crossbar Memories

Ioannis Vourkas, Dimitrios Stathis, Georgios Ch. Sirakoulis, Said Hamdioui
<span title="">2016</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
MEMRISYS2015 Extended Abstract The memristor represents one of today's latest technological achievements in circuits and systems, demonstrating advantageous characteristics which open new pathways for  ...  or logic gates [5], [6], [7], [8], [9].  ...  A simulation-based validation of read/write memory operations as well as of parallel memristive logic computations (half adder, sum of products, etc.) is performed using the PSPICE simulation environment  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2015.2388587">doi:10.1109/tvlsi.2015.2388587</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/vtatytf4kbdxrkhsuvyoxfy2tq">fatcat:vtatytf4kbdxrkhsuvyoxfy2tq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180724064254/https://upcommons.upc.edu/bitstream/handle/2117/104852/M2015.pdf;jsessionid=49A87F2EEBA91F303CEB9BAC3386EDBD?sequence=3" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/6b/f7/6bf7e16febfa0b38c13c49ba9a83cea6ff460266.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2015.2388587"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Adaptive Distributed Genetic Algorithms And Its Vlsi Design

Kazutaka Kobayashi, Norihiko Yoshida, Shuji Narazaki
<span title="2009-04-22">2009</span> <i title="Zenodo"> Zenodo </i> &nbsp;
This paper presents a dynamic adaptation scheme for the frequency of inter-deme migration in distributed genetic algorithms (GA), and its VLSI hardware design.  ...  Through simulation experiments, we proved that our scheme achieves better performance than fixed frequency migration schemes.  ...  We carried out logic simulation and logic synthesis for preliminary evaluation of the design prior to actual VLSI fabrication.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5281/zenodo.1328805">doi:10.5281/zenodo.1328805</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/cdnar75dyzgxvnjloo6l32c2cq">fatcat:cdnar75dyzgxvnjloo6l32c2cq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200309050719/https://zenodo.org/record/1328806/files/645.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/5a/70/5a700be973f5a7c41fae9ba29298580832944705.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5281/zenodo.1328805"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> zenodo.org </button> </a>

Implementation of Circuit Optimization Technique for Digital CMOS Comparator Using Parallel Prefix Tree Architecture

P. Ranjith, P. Shankar Bharathi
<span title="">2014</span> <i title="IOSR Journals"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/7ftgkqdzrnfspfyjn3usmdd66q" style="color: black;">IOSR Journal of VLSI and Signal processing</a> </i> &nbsp;
The tanner EDA tool simulation for 16-bit is realized using 0.18-µm CMOS process technology with minimum supply voltage of 2.45V. I.  ...  The digital comparator using CMOS cells that adopts the parallel prefix tree architecture.  ...  Model Used The improved system is realized as [2] using tanner EDA simulation tool V7.0 1.25µm technology model file ml2_125.md with minimum supply voltage of 2.5V. D.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.9790/4200-04219698">doi:10.9790/4200-04219698</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/54yq3px4pbabxlebkvtv5knu7m">fatcat:54yq3px4pbabxlebkvtv5knu7m</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180601225537/http://www.iosrjournals.org/iosr-jvlsi/papers/vol4-issue2/Version-1/O04219698.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/4b/d6/4bd67c5482916f6a916b555a5332fb075b1dd719.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.9790/4200-04219698"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Design of Prefix Adder Amalgamation Reversible Logic Gates using 16 Bit Kogge Stone Adder

P. Michael Preetam Raj, Bhaskaruni Sandeep, D. Sai Mallik Reddy, P. Ramanjaneyulu, Sakhamuri Sai Pravallika
<span title="2016-04-22">2016</span> <i title="Indian Society for Education and Environment"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/wffwpj3q45g5zfjzfeyagk5uea" style="color: black;">Indian Journal of Science and Technology</a> </i> &nbsp;
Methods/Analysis: Design of the delay models and cost analysis by VLSI embedded system is done in this paper.  ...  Findings: Methodology is based on the fact that a parallel prefix adder can be represented as a graph consists of carry operator nodes.  ...  This paper proposed design reduces the power consumption and cost analysis for development of VLSI, Embedded Systems in real time technology.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.17485/ijst/2016/v9i13/87911">doi:10.17485/ijst/2016/v9i13/87911</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xciqify2tbhurfnjt3xz7o4lny">fatcat:xciqify2tbhurfnjt3xz7o4lny</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180720062530/http://www.indjst.org/index.php/indjst/article/download/87911/68556" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.17485/ijst/2016/v9i13/87911"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

A Cellular Automaton Crowd Tracking System for Modelling Evacuation Processes [chapter]

Ioakeim G. Georgoudas, Georgios Ch. Sirakoulis, Ioannis Th. Andreadis
<span title="">2006</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
The system comprises three stages: The system comprises three stages:  ...  tracking system The hardware part includes: The hardware part includes: • • VLSI realization of the CA model VLSI realization of the CA model • • Sound Sound--optical notification system optical  ...  The CA The CA--based Simulation Model based Simulation Model The model simulates prominent features of crowd The model simulates prominent features of crowd behaviour during evacuation of a closed area  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/11861201_82">doi:10.1007/11861201_82</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/pr4ghlqvrnga7p6wdp4fpjq7me">fatcat:pr4ghlqvrnga7p6wdp4fpjq7me</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170809054233/http://www.lintar.disco.unimib.it/space/Eventi/CandCA/4-cca06-georgoudas.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f0/bc/f0bc023989c5a3261cc8a81fbc90a80a2555bd6c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/11861201_82"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>
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