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Parallel FPGA-based all-pairs shortest-paths in a directed graph

U. Bondhugula, A. Devulapalli, J. Fernando, P. Wyckoff, P. Sadayappan
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
In this paper, we propose a highly parallel FPGA design for the Floyd-Warshall algorithm to solve the allpairs shortest-paths problem in a directed graph.  ...  With rapid advances in VLSI technology, Field Programmable Gate Arrays (FPGAs) are receiving the attention of the Parallel and High Performance Computing community.  ...  The all-pairs shortest-paths problem is to find a shortest path between each pair of vertices in a weighted directed graph.  ... 
doi:10.1109/ipdps.2006.1639347 dblp:conf/ipps/BondhugulaDFWS06 fatcat:ngqqy36z6fekbp5exf2clrwksa

Accelerating all-pairs shortest path using a message-passing reconfigurable architecture

Osama G. Attia, Alex Grieve, Kevin R. Townsend, Phillip Jones, Joseph Zambreno
2015 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)  
We take advantage of our architecture to showcase a parallel implementation of the all-pairs shortest path algorithm (APSP) for unweighted directed graphs.  ...  In this paper, we study the design and implementation of a reconfigurable architecture for graph processing algorithms.  ...  ACKNOWLEDGMENT This work was supported in part by the National Science Foundation (NSF), under awards CNS-1116810 and CCF-1149539.  ... 
doi:10.1109/reconfig.2015.7393284 dblp:conf/reconfig/AttiaGTJZ15 fatcat:aqg3676dvrcinaxmpgjj5nhq4y

Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths

Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan
2006 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines  
We address this hardware/software integration challenge in the context of the All-Pairs Shortest-Paths (APSP) problem in a directed graph.  ...  We employ a parallel FPGA-based design using a blocked algorithm to solve large instances of APSP.  ...  The all-pairs shortest-paths problem is to find a shortest path between each pair of vertices in a weighted directed graph.  ... 
doi:10.1109/fccm.2006.48 dblp:conf/fccm/BondhugulaDDFWSS06 fatcat:55winkha65hqvcw3wvehv7elsa

Hardware computing for brain network analysis

Yu Wang, Yong He, Yi Shan, Tianji Wu, Di Wu, Huazhong Yang
2010 2nd Asia Symposium on Quality Electronic Design (ASQED)  
Recent studies have suggested a noninvasive way of modeling and analyzing the human cortical networks with MRI by graph theory based approaches.  ...  Designing platforms for specific applications using the reconfigurable logic such as Field Programmable Gate Arrays (FPGAs) or highly parallel processors such as Graphic Processing Units (GPUs) will dramatically  ...  In [21] , several fundamental graph algorithms are implemented on GPU, such as breadth first search, single source shortest path, and all-pairs shortest path.  ... 
doi:10.1109/asqed.2010.5548242 fatcat:hne54kgrwve2lpe6njsmsnq4li

PEFP: Efficient k-hop Constrained s-t Simple Path Enumeration on FPGA [article]

Zhengmin Lai, You Peng, Shiyu Yang, Xuemin Lin, Wenjie Zhang
2021 arXiv   pre-print
On the FPGA side in PEFP, we propose a novel DFS-based batching technique to save on-chip memory efficiently.  ...  Finally, we propose a data separation technique to enable dataflow optimization for the path verification module; hence the sub-stages in that module can be executed in parallel.  ...  [28] proposed to solve all-pairs-shortestpaths (APSP) problem on FPGA, which is to find shortest path between all pairs of vertices in the graph.  ... 
arXiv:2012.11128v2 fatcat:wlwbhd7d6fdrpjoc4g3tklmq5e

Graph Processing on FPGAs: Taxonomy, Survey, Challenges [article]

Maciej Besta, Dimitri Stanojevic, Johannes De Fine Licht, Tal Ben-Nun, Torsten Hoefler
2019 arXiv   pre-print
This is reflected by the recent interest in developing various graph algorithms and graph processing frameworks on FPGAs.  ...  Finally, we discuss research and engineering challenges to outline the future of graph computations on FPGAs.  ...  All-Pairs Shortest-Paths (APSP). The All-Pairs Shortest-Paths (APSP) problem is to find the shortest paths between all pairs of vertices in the graph.  ... 
arXiv:1903.06697v3 fatcat:f5usapd45jgqpf7ynlz4w6e4si

Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform

Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid
2013 International Journal of Reconfigurable Computing  
The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set of constraints to be taken into account during the partitioning task.  ...  Multi-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle.  ...  The idea is to assign, according to criteria to be detailed later, a definite direction to all physical wires. In the routing graph, this is translated by a single edge between each pair of nodes.  ... 
doi:10.1155/2013/853510 fatcat:syot452tdzdgxieiss4zdfwppy

Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs

Dinesh P. Mehta, Carl Shetters, Donald W. Bouldin
2013 VLSI design (Print)  
GPRM, the more general of the two schemes, reduces the problem to computing a shortest path in a DAG; SPRM, the less general scheme, employs dynamic programming.  ...  This paper considers the problem of scheduling a chain ofncoarse-grained tasks on a linear array ofkreconfigurable FPGAs with the objective of primarily minimizing reconfiguration time.  ...  The same approach can be used in GPRM: if there are a pair of consecutive configurations (represented by vertices joined by a directed edge in the shortest-path graph) such that the output of a task in  ... 
doi:10.1155/2013/249592 fatcat:l3lksw3ebzfz5hge6ea6ij7yfa

Dynamic programming on a functional memory computer

A. Lew, R. Halverson
1999 Computers and Mathematics with Applications  
As specific examples, we showed how the HPC can be used to implement dynamic programming solutions of shortest-path and traveling-salesman problems.  ...  ln a previous paper [I], we described the solution of dynamic programming problems on a new class of parallel processing systems, the Hawaii Parallel Computer (HPC).  ...  Nondeterministic versions of dynamic programming algorithms, such as those for finding the shortest path in a cyclic graph and for finding the shortest cyclic path traversing all nodes once (the traveling-salesman  ... 
doi:10.1016/s0898-1221(99)00138-8 fatcat:ccej5jnjircajidlfsgigdhfb4

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Pablo Dopazo, Carola de Benito, Oscar Camps, Stavros G. Stavrinides, Rodrigo Picos
2021 Physics  
In this paper, a system exploring the optimal paths through a maze, utilizing a memristor-based setup, is developed and concreted on a FPGA (field-programmable gate array) device.  ...  The operation of the algorithm in the MATLAB (matrix laboratory) programming enviroment is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA  ...  The FPGA's returned result in the case of a 4 × 4 maze. The corresponding recovered shortest path (nodes in green) appears, showing the directions in Figure 8, according to Table2.  ... 
doi:10.3390/physics4010001 fatcat:ytvrxyi2qjborapwqzk7illwti

Language and hardware acceleration backend for graph processing

Andrey Mokhov, Alessandro de Gennaro, Ghaith Tarawneh, Jonny Wray, Georgy Lukyanov, Sergey Mileiko, Joe Scott, Alex Yakovlev, Andrew Brown
2017 2017 Forum on Specification and Design Languages (FDL)  
This eliminates the memory bottleneck and allows thousands of vertices to be processed in parallel.  ...  We present a domainspecific language for graph description and transformation, and demonstrate how it can be used to translate application graphs into an FPGA board, where they can be analysed 1000x faster  ...  For unweighted graphs, which are typically used in the drug discovery context, a breadth-first search is the most efficient solution to obtain all shortest paths between a pair of vertices with a time  ... 
doi:10.1109/fdl.2017.8303899 dblp:conf/fdl/MokhovGTWLMSYB17 fatcat:nurwcivyvnfrhfmneckdiigae4

Incremental compilation for parallel logic verification systems

R. Tessier, S. Jana
2002 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we describe and analyze a set of incremental compilation steps that can be directly applied to a range of parallel logic verification hardware, including logic emulators.  ...  To validate our incremental compilation techniques, the developed mapping heuristics have been integrated into the compilation flow for a field-programmable gate-array-based Ikos VirtuaLogic emulator [  ...  To evaluate our system, initial RTL implementations of both a standard shortest path (ssp64) and multiplicative shortest path (spm16) graph were created using tools from the RAW benchmark suite [24] .  ... 
doi:10.1109/tvlsi.2002.801614 fatcat:r6l3cna55zbsvc2jcnrj7bhiju

Shortest Path Search Algorithm in Optimal Two-Dimensional Circulant Networks: Implementation for Networks-on-Chip

Emilia A. Monakhova, Aleksandr Yu. Romanov, Evgenii V. Lezhnev
2020 IEEE Access  
More precisely, a total number of all the shortest paths for is (| | | |) (| | | | ).  ...  Further in the article, we assume the undirected store-and-forward model. The organization of pair exchanges requires determination of the shortest paths in a graph.  ... 
doi:10.1109/access.2020.3040323 fatcat:kwilk2dby5hrrkrk4bwotib7ri

Non-Relational Databases on FPGAs: Survey, Design Decisions, Challenges [article]

Jonas Dann, Daniel Ritter, Holger Fröning
2020 arXiv   pre-print
For example, we found in the literature that for key-value stores the FPGA should be placed into the system as a smart network interface card (SmartNIC) to benefit from direct access of the FPGA to the  ...  such a system with FPGAs.  ...  Acknowledgements We thank Norman May and Wolfgang Lehner for various valuable discussions in the context of this article.  ... 
arXiv:2007.07595v1 fatcat:eganwap76ffpzbl6fztprecawq

GraphStep: A System Architecture for Sparse-Graph Algorithms

Michael deLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas Uribe, Thomas Jr. Knight, Andre DeHon
2006 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines  
To avoid this "memory wall," we introduce a concurrent system architecture for sparse graph algorithms that places graph nodes in small distributed memories paired with specialized graph processing nodes  ...  On typical spreadingactivation queries on the ConceptNet Knowledge Base, a sample application, this translates into an order of magnitude speedup per FPGA compared to a state-of-the-art Pentium processor  ...  Pathfinder [17] ) is based on a series of shortest path searches.  ... 
doi:10.1109/fccm.2006.45 dblp:conf/fccm/DeLorimierKMRERUKD06 fatcat:nhs4imph3rdnljnn5sslljioeu
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