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Parallel evaluation of arithmetic circuits

Nathalie Revol, Jean-Louis Roch
1996 Theoretical Computer Science  
In this paper, a generic algorithm designed for the parallel evaluation of arithmetic circuits is given.  ...  More generally, the (theoretical) algorithm presented in Section 2 evaluates very quickly arithmetic straight-line programs, and its evaluation time serves as a good upper bound.  ...  Thus, any parallel computation is equivalent to the parallel evaluation of the corresponding boolean circuit.  ... 
doi:10.1016/0304-3975(95)00252-9 fatcat:tvpa7uxndbdrxfob73ywnsaut4

Efficient parallel evaluation of straight-line code and arithmetic circuits [chapter]

Gary L Miller, Vijaya Ramachandran, Erich Kaltofen
1986 Lecture Notes in Computer Science  
We consider two basically equivalent models of evaluation over a semi-ring: straight-line programs and arithmetic circuits.  ...  Key words, parallel computation, straight-line code, arithmetic circuits AMS(MOS) subject classifications. 68Q40, 68Q35, 68Q25 1. Introduction.  ...  t Mathematical Sciences Research Institute and Department of Computer Science, University of Southern California, Los Angeles, California 90089-0782.  ... 
doi:10.1007/3-540-16766-8_21 fatcat:ady4uf7okbcs5c66sdm54vqhrm

Efficient Parallel Evaluation of Straight-Line Code and Arithmetic Circuits

Gary L. Miller, Vijaya Ramachandran, Erich Kaltofen
1988 SIAM journal on computing (Print)  
A new parallel algorithm is given to evaluate a straight-line program.  ...  The algorithm evaluates a program over a commutative semi-ring R of degree d and size n in time O((Iog n)(log nd)) using M(n) processors, where M(n) is the number of processors required for multiplying  ...  On the other hand, Valiant, Skyum, Berkowitz, and Rackoff gave a Top-Down parallel algorithm for arithmetic circuit evaluation [VSBR]; in this paper, we give a Bottom-Up parallel algorithm for this problem  ... 
doi:10.1137/0217044 fatcat:uczqfkiriffe7fk3sdlioitcky

A Parallel Circuit Simulator for Iterative Power Grids Optimization System

Taiki Hashizume, Masaya Yoshikawa, Masahiro Fukui
2012 Circuits and Systems  
This paper discusses a high efficient parallel circuit simulator for iterative power grid optimization. The simulator is implemented by FPGA.  ...  We focus particularly on the following points: 1) Selection of the analysis method for power grid optimization, the proposed simulator introduces hardware-oriented fixed point arithmetic instead of floating  ...  Evaluation of Parallel Processing This section described parallel processing of the power grid simulation. The simulation module by pipeline processing in previous section is connected in parallel.  ... 
doi:10.4236/cs.2012.32020 fatcat:rctixw4nsfczxezgiykr2s7bya

A parallel method for fast and practical high-order newton interpolation

Ö. EĞecioĞlu, E. Gallopoulos, Ç. K. Koç
1990 BIT Numerical Mathematics  
We present parallel algorithms for the computation and evaluation of interpolating polynomials.  ...  For n + 1 given input pairs, the proposed interpolation 2 algorithm requires only 2 Flog(n + 1)] + 2 parallel arithmetic steps and circuit size O(n ), reducing the best known circuit size for parallel  ...  The Newton interpolating polynomial of degree n can be evaluated in 2 Vlog(n + 1)] + 2 parallel arithmetic steps using n processors and can be implemented as an arithmetic circuit of size O(n).  ... 
doi:10.1007/bf02017348 fatcat:orii44aerbedjdh3b4nn6wg4na

1983 Index IEEE Transactions on Computers Vol. C-32

1983 IEEE transactions on computers  
., + , T-CJul 83 621-637 arithmetic design system to support quantitative evaluation of alternate number systems.  ...  Computer architecture Arithmetic arithmetic design system to support quantitative evaluation of alternate number systems. Ong, Shauchi, + , T-CApr 83 359-369 computer arithmetic (special issue).  ... 
doi:10.1109/tc.1983.1676190 fatcat:xsogjoynp5dt7mqu6dy4tiodfq

Fine-grained parallelization of fitness functions in bioinformatics optimization problems: gene selection for cancer classification and biclustering of gene expression data

Juan A. Gomez-Pulido, Jose L. Cerrada-Barrios, Sebastian Trinidad-Amado, Jose M. Lanza-Gutierrez, Ramon A. Fernandez-Diaz, Broderick Crawford, Ricardo Soto
2016 BMC Bioinformatics  
of the arithmetic operations, but also thanks to the concurrent fitness evaluation for several individuals of the population in the metaheuristic.  ...  This way, a careful parallelization of these functions using the reconfigurable hardware technology will accelerate the computation, specially if they are applied in parallel to several solutions of the  ...  circuits evaluate individuals in parallel, taking into account the area constraints for a single FPGA.  ... 
doi:10.1186/s12859-016-1200-9 pmid:27581798 pmcid:PMC5007680 fatcat:i26tgdgnfvhrvhufxx7hfsuazm

Size-depth trade-offs for monotone arithmetic circuits

Marc Snir
1991 Theoretical Computer Science  
A the evaluation of linear recurrences.  ...  We show that the size s and depth d of monotone arithmetic circuits for this problem are related as s + n3d = R( tn.')  ...  in 0( n') operations, y (monotone) arithmetic circuit of sublinear at evaluates p must uction in circuit notone transformacantly increase the circuit six.  ... 
doi:10.1016/0304-3975(91)90173-y fatcat:nn52764ewjaknaawxnau47z64i

A Processor With Dynamically Reconfigurable Circuit For Floating-Point Arithmetic

Yukinari Minagi, Akinori Kanasugi
2010 Zenodo  
This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor.  ...  The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754.  ...  Each circuit reconfigures two modes as indicated by the following: (i) One double precision floating-point arithmetic, (ii) Two parallel operations of single precision floating-point arithmetic.  ... 
doi:10.5281/zenodo.1080514 fatcat:cnjbir5rtrfmpn7tbrmb2qfrcq

Automatic Generation System for Multiple-Valued Galois-Field Parallel Multipliers

Rei UENO, Naofumi HOMMA, Takafumi AOKI
2017 IEICE transactions on information and systems  
This paper presents a system for the automatic generation of Galois-field (GF) arithmetic circuits, named the GF Arithmetic Module Generator (GF-AMG).  ...  In addition, we evaluate the performance of three types of GF(2 m ) multipliers and typical GF(p m ) multipliers (p ≥ 3) empirically generated by our system.  ...  Galois-Field Arithmetic Circuit Graph Definition of Galois-Field Arithmetic Circuit Graph Figure 1 shows an overview of the GF-ACG.  ... 
doi:10.1587/transinf.2016lop0010 fatcat:s3jikfwk3rcydb5o2ybrcvoiru

Compiling Low Depth Circuits for Practical Secure Computation [chapter]

Niklas Buescher, Andreas Holzer, Alina Weber, Stefan Katzenbeisser
2016 Lecture Notes in Computer Science  
With the rise of practical Secure Multi-party Computation (MPC) protocols, compilers have been developed that create Boolean or Arithmetic circuits for MPC from functionality descriptions in a highlevel  ...  Previous compilers focused on the creation of size-minimal circuits. However, many MPC protocols, such as GMW and SPDZ, have a round complexity that is dependent on the circuit's depth.  ...  Acknowledgments This work has been co-funded by the DFG as part of project S5 within the CRC 1119 CROSSING, by the DFG as part of project A.1 within the RTG 2050 "Privacy and Trust for Mobile User", and  ... 
doi:10.1007/978-3-319-45741-3_5 fatcat:jp4ltdj7vfeo3e3m5mwhdjufrq

Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit

Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A Kulkarni, Bhagyalakshmi H.R, Venkatesha M.K
2013 International Journal of VLSI Design & Communication Systems  
Significant contributions have been made in the literature towards the design of fault tolerant reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards  ...  the design of fault tolerant reversible ALUs.  ...  ACKNOWLEDGEMENTS The authors would like to thank Department of Electronics and Communication, B.M.S. College of Engineering, Bangalore India for supporting this work.  ... 
doi:10.5121/vlsic.2013.4306 fatcat:oivcsbjp45edpb3twwpegpwy2m

Formal Design of Arithmetic Circuits over Galois Fields Based on Normal Basis Representations

Kotaro OKAMOTO, Naofumi HOMMA, Takafumi AOKI
2014 IEICE transactions on information and systems  
In addition, we design GF exponentiation circuits consisting of the Massey-Omura parallel multipliers and an inversion circuit over composite field GF(((2 2 ) 2 ) 2 ) in order to demonstrate the advantages  ...  The proposed method is based on a graph-based circuit description called Galois-field Arithmetic Circuit Graph (GF-ACG).  ...  Nogami of Okayama University for his valuable advice about the normal basis theory.  ... 
doi:10.1587/transinf.2013lop0012 fatcat:sn3qb24klvbl3ijtabmjoj3mae

Arithmetic module generator with algorithm optimization capability

Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2008 2008 IEEE International Symposium on Circuits and Systems  
The use of ARITH makes it possible to describe a wide variety of arithmetic algorithms in a unified manner.  ...  In this paper, we demonstrate that the optimal prefix adders improved the performance of generated arithmetic modules such as multipliers in comparison with the standard prefix adders.  ...  The proposed formal method consists of "formula evaluation" and "range evaluation." The ARITH code holds correct arithmetic circuit structures if and only if both evaluations return true.  ... 
doi:10.1109/iscas.2008.4541788 dblp:conf/iscas/WatanabeHAH08 fatcat:aoeywmcrpbhmfoeobic77bcjwq

Homomorphically Encrypted Computation using Stochastic Encodings [article]

Hsuan Hsiao, Vincent Lee, Brandon Reagen, Armin Alaghi
2022 arXiv   pre-print
For even heavily quantized fixed-point arithmetic operations, these HE circuit implementations can be slow.  ...  For instance, in Boolean constructions of HE like TFHE, arithmetic operations need to be decomposed into constituent elementary logic gates to implement so performance depends on logical circuit depth.  ...  Evaluation To explore the merits and limitations of SCHE, we evaluate the performance, accuracy, and the impact of SIMD parallelization.  ... 
arXiv:2203.02547v1 fatcat:57h6cyxqhrgkdmgl6tn7mpk3uy
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