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An address translation simulator

Steven Robbins
2005 Proceedings of the 36th SIGCSE technical symposium on Computer science education - SIGCSE '05  
The address translation simulator described here solves this problem by presenting the student with complete page tables in a way that allows simple navigation of these tables.  ...  When examples are given, only a piece of the translation is done, using a small translation lookaside buffer or a small single-level page table.  ...  The user is presented with an address translation problem in a window like the one shown in Figure 6 . The page size is 4K bytes, the virtual address is 30 bits, and the physical address is 23 bits.  ... 
doi:10.1145/1047344.1047507 dblp:conf/sigcse/Robbins05 fatcat:bp6was6znvcwvpsdrol3vmkc4m

An address translation simulator

Steven Robbins
2005 ACM SIGCSE Bulletin  
The address translation simulator described here solves this problem by presenting the student with complete page tables in a way that allows simple navigation of these tables.  ...  When examples are given, only a piece of the translation is done, using a small translation lookaside buffer or a small single-level page table.  ...  The user is presented with an address translation problem in a window like the one shown in Figure 6 . The page size is 4K bytes, the virtual address is 30 bits, and the physical address is 23 bits.  ... 
doi:10.1145/1047124.1047507 fatcat:cicpkd3zgfgxjaf2lk2tgnamwe

An in-cache address translation mechanism

D. A. Wood, S. J. Eggers, G. Gibson, M. D. Hill, J. M. Pendleton
1986 SIGARCH Computer Architecture News  
Eliminating the TLB substantially reduces the hardware cost and complexity of the translation mechanism and eliminates the translation consistency problem.  ...  In the design of SPUR, a high-performance multiprocessot workstation, the use of large caches and hardware-supported cache consistency suggests a new approach to virtual address translation.  ...  Additional support was provided by Texas Instruments and the California MICRO program. References  ... 
doi:10.1145/17356.17398 fatcat:2mtazkotlbgnnco2movpstvsdy

Standalone verification of IOMMU with virtualization supporting

A.A. Petrykin, I.A. Stotland, A.N. Meshkov
2019 Proceedings of the Institute for System Programming of RAS  
For native translation, the address of the first line is formed from the host page table index (hptp) contained in the DTE, and a part of the translated virtual address.  ...  Then the GP_L4 page itself is written and after that the guest physical address of the next page level (GPA_3) is calculated as the sum of HP_L1 page ppn and part of virtual address: = + (3) (3) And so  ... 
doi:10.15514/ispras-2019-31(3)-7 fatcat:yausl6soknatndfm2yqmk5yhda

Translation-lookaside buffer consistency

P.J. Teller
1990 Computer  
Also, my thanks to the other researchers who have addressed the problem of TLB consistency, without whom this paper would not be possible, and to Susan Flynn-Hummel, Bryan Rosenburg, and Edith Schonberg  ...  Acknowledgments Many thanks to the referees and Michel Dubois. whose constructive criticism shaped the final form of this paper, and to Harold Stone for much helpful advice.  ...  Physical address The problem of TLB consistency Frame number Linenumber I i:f :e More than one image of apage's translation information can exist: one is stored in the page table and others can be stored  ... 
doi:10.1109/2.55498 fatcat:2ab6fhw32jb4niwjo2viyxupg4

Addressing Mechanisms for Large Virtual Memories

J. Rosenberg, J. L. Keedy, D. Abramson
1992 Computer journal  
This paper presents hardware and software mechanisms to implement a paged virtual memory which can be efficiently accessed by large addresses.  ...  In such systems arbitrary data structures may persist beyond the life of the program which created them and this distinction is blurred.  ...  Their constructive comments and suggestions have resulted in substantial improvements to the paper.  ... 
doi:10.1093/comjnl/35.4.369 fatcat:spljagy4tfdobhmmclgf7fymfi

Page 82 of Behavior Research Methods Vol. 7, Issue 2 [page]

1975 Behavior Research Methods  
The overlays must always be in the same place to avoid address translation. If the overlays contain only data, as in large arrays, there is no address translation problem.  ...  This solution takes more space and has some position-independent code which is harder to produce. It also suffers from severe overheads for the demand-paging and address translation.  ... 

Virtual-address caches. Part 1: problems and solutions in uniprocessors

M. Cekleov, M. Dubois
1997 IEEE Micro  
In general, consistency problems in virtual-address caches are due to synonyms and to address-mapping changes. Synonym problem.  ...  page tables Physical address: Address in physical memory obtained after translation of the virtual address in the page tables P/P cache: Physical cache indexed and tagged with bits from the physical address  ... 
doi:10.1109/40.621215 fatcat:uaztemiztbgqdmmja34qd5jnca

3DFTL: a three-level demand-based translation strategy for flash device

Peera Thontirawong, Chundong Wang, Weng-Fai Wong, Mongkol Ekpanyapong, Prabhas Chongstitvatana
2015 IEICE Electronics Express  
3DFTL is a demand-based flash translation layer (demand-based FTL) that can withstand caching data loss due to unexpected events such as power-loss.  ...  As a result, not only the mapping table of 3DFTL guarantees data consistency, but 3DFTL also shows 16.42% decrease in terms of the average system response time comparing with the DFTL.  ...  As a result, the whole operation becomes non-atomic, and an inconsistency problem between data pages and translation pages is arisen.  ... 
doi:10.1587/elex.12.20150211 fatcat:5eg3gikpxrgnlpcouxghy4cj3a

Anticipatory I/O Management for Clustered Flash Translation Layer in NAND Flash Memory

Kwanghee Park, Junsik Yang, Joon-Hyuk Chang, Deok-Hwan Kim
2008 ETRI Journal  
Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive  ...  It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique.  ...  If it finds a matching LBA in Traditional Hashing Problems Basically, most FTLs and the address translation scheme in virtual memory use hash tables to translate logical addresses into physical addresses  ... 
doi:10.4218/etrij.08.0108.0145 fatcat:fzre3oo6crgnxnwi7to3jqvh6y

Supporting superpages in non-contiguous physical memory

Yu Du, Miao Zhou, Bruce R. Childers, Daniel Mosse, Rami Melhem
2015 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)  
To further compress the page table and improve cache hit rates for address translation in large memory footprint workloads, we also propose an extended format that reduces the page table size by 50%.  ...  To address this problem, we propose GTSM, or gaptolerant sequential mapping, that allows superpages to be formed even in the presence of retired physical pages.  ...  Gap-tolerant Page Directory Entry (GT-PDE) For a 2MB superpage, PDE (page directory entry) is the last level of address translation; the PDE format contains the physical page frame base address and control  ... 
doi:10.1109/hpca.2015.7056035 dblp:conf/hpca/DuZCMM15 fatcat:x4oc3juy7jfthg44ztryj3uc5q

A "network-paging" based method for wide-area live-migration of VMs

Yasusi Kanada, Toshiaki Tarui
2011 The International Conference on Information Networking 2011 (ICOIN2011)  
One is to switch an address-translation rule, and the other is to switch multiple virtual networks.  ...  The former is analogous to paging in memory virtualization, and the latter is analogous to segmentation. The "network-paging" based method is described and our evaluation results are shown.  ...  Address-translation-based method and "network-paging" The address mapping used in this method is shown in Fig. 4 .  ... 
doi:10.1109/icoin.2011.5723191 dblp:conf/icoin/KanadaT11 fatcat:mqlvtl4c2jh45og5asnp5tcv4i

Virtual address translation for wide-address architectures

Ing-Jye Shyu, Shiuh-Pyng Shieh
1995 ACM SIGOPS Operating Systems Review  
In conventional virtual memory management systems, both the forwardmapped page table scheme and inverted page table scheme are widely used to organize the page tables that record translation data.  ...  To cope with this problem, we propose a hybrid scheme to accelerate wide virtual address translation.  ...  .: Base Address, Figure 5 " 5 Hybrid translation schemel Address aliasing is another problem of using inverted page table.  ... 
doi:10.1145/219282.219290 fatcat:q4wws4zrerdqnlxsved7nxuqn4

Efficient memory virtualization for Cross-ISA system mode emulation

Chao-Jui Chang, Jan-Jan Wu, Wei-Chung Hsu, Pangfeng Liu, Pen-Chung Yew
2014 SIGPLAN notices  
hardware for address translation.  ...  ARM and x86 Shadow Page Table 7 1: James Smith, "Virtual Machines: Versatile Platforms for Systems and Processors" • Access guest memory directly -Let MMU hardware be aware of the guest addresses  ... 
doi:10.1145/2674025.2576201 fatcat:cbyr6bjkzncfta3hxqr6v2k7k4

The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches

Xiaogang Qiu, M. Dubois
2008 IEEE transactions on computers  
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB).  ...  The SLB translates synonyms into a primary virtual address, which is a unique identifier resolving all ambiguities due to synonyms in the memory system.  ...  In the first step, the virtual page number is translated in the TLB and the tags and data of the first-level cache set are fetched (cache set indexing).  ... 
doi:10.1109/tc.2008.108 fatcat:c6lyqm76njblhbqtukzfmsmtfq
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