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Packet Triggered Prediction Based Task Migration for Network-on-Chip

Chao Wang, Licheng Yu, Li Liu, Tianzhou Chen
2012 2012 20th Euromicro International Conference on Parallel, Distributed and Network-based Processing  
Choose triggering mechanism • Migrations start after sample periods when enough information is collected to predict network behavior afterwards.  ...  Method to divide the periods is also the trigger for initiating migrations. • SNP (Single Node Packet) denotes that when the amount of packets sent by any node (to which a specified task is mapped) reaches  ...  Define a quantitative way to analyze the predictability of real applications. 2. Compare different triggers for migration. 3.  ... 
doi:10.1109/pdp.2012.37 dblp:conf/pdp/WangYLC12 fatcat:ejpv5iqsq5bsdmd4om7fc3xbsm

An Artificial Neural Networks based Temperature Prediction Framework for Network-on-Chip based Multicore Platform [article]

Sandeep Aswath Narayana
2016 arXiv   pre-print
Moreover, the typical DTM is triggered reactively based on temperature measurements from on-chip thermal sensor requiring long reaction times whereas predictive DTM method estimates future temperature  ...  This thesis concentrates on designing an ANN prediction engine to predict the thermal profile of the cores and Network-on-Chip elements of the chip.  ...  Task migration redistributes existing processes to available cores based on the current thermal profile of the chip. Runtime task migration is a popular technique for reducing peak temperature.  ... 
arXiv:1612.04197v1 fatcat:uoyot2zhwvfq7kigsqy5avruei

Thermal prediction and scheduling of network applications on multicore processors

Chih-Hsun Chou, Mehmet E. Belviranli, Laxmi N. Bhuyan
2013 Architectures for Networking and Communications Systems  
As processor power density increases, chip/core temperature control becomes critical for building multicore systems.  ...  This paper addresses the problem of inter-core thermal coupling and periodic thermal variation while executing multi-threaded network applications in a multicore architecture.  ...  Stop&GO and Thread migration, when the temperature reaches the trigger temperature, and is based on our predictive thermal model and the core/cache activity recorded by the thread monitor.  ... 
doi:10.1109/ancs.2013.6665188 dblp:conf/ancs/ChouBB13 fatcat:arleyyy6pnaebb2tj4jqonqwga

Hardware task migration module for improved fault tolerance and predictability

Shyamsundar Venkataraman, Rui Santos, Akash Kumar, Jasper Kuijsten
2015 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
This paper proposes a hardware-based task migration scheme for MPSoC systems, offering better predictability as well as an improved method of fault tolerance.  ...  Task migration has been applied as an efficient mechanism to handle faulty processing elements (PEs) in Multiprocessor Systems-on-Chip (MPSoCs).  ...  Architecture Model A mesh-based Network-on-Chip (NoC) architecture has been used for this research.  ... 
doi:10.1109/samos.2015.7363676 dblp:conf/samos/VenkataramanSKK15 fatcat:ckrqqluzdbfrtemkx3jqedcscy

Distributed task migration for thermal management in many-core systems

Yang Ge, Parth Malani, Qinru Qiu
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
In this paper, we propose a framework for distributed thermal management for many-core systems where balanced thermal profile can be achieved by proactive task migration among neighboring cores.  ...  The framework has a low cost agent residing in each core that observes the local workload and temperature and communicates with its nearest neighbor for task migration/exchange.  ...  All the processors and routers are connected by an on-chip network where information is communicated via packet transmission.  ... 
doi:10.1145/1837274.1837417 dblp:conf/dac/GeMQ10 fatcat:chwwtjyl2zhzdldbq5kfmruq4m

Adaptation Strategies in Multiprocessors System on Chip [chapter]

Remi Busseuil, Gabriel Marchesan Almeida, Luciano Ost, Sameer Varyani, Gilles Sassatelli, Michel Robert
2012 IFIP Advances in Information and Communication Technology  
Multi-processor System-on-Chips (MPSoCs) have become increasingly popular over the past decade.  ...  Task migration permits balancing load among the several processors the system is made of.  ...  The network layer consists of a light router based on the Hamiltonian Routing Algorithm [47] . The Network on Chip is derived from [48] .  ... 
doi:10.1007/978-3-642-28566-0_10 fatcat:lqxg2ujikndgjjvnxrli6x5cza

A Multi-Agent Framework for Thermal Aware Task Migration in Many-Core Systems

Yang Ge, Qinru Qiu, Qing Wu
2012 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The framework has a low cost agent residing in each core that observes the local workload and temperature and communicates with its nearest neighbor for task migration and exchange.  ...  In this paper, we propose a framework for distributed thermal management in many-core systems where balanced thermal profile can be achieved by proactive task migration among neighboring cores.  ...  All the processors and routers are connected by an on-chip network where information is communicated via packet transmission.  ... 
doi:10.1109/tvlsi.2011.2162348 fatcat:vxztslr67jfujkojv4smitsyeu

Explicit Communication and Synchronization in SARC

Manolis Katevenis, Vassilis Papaefstathiou, Stamatis Kavadias, Dionisios Pnevmatikatos, Federico Silla, Dimitrios Nikolopoulos
2010 IEEE Micro  
packets, and the processor should not wait for the arrival acknowledgments.  ...  The on-chip network provides efficient communication among these configurable memories, using advanced topologies and routing algorithms, and providing for process variability in NoC links.  ...  This work was supported by the European Commission in the context of the project SARC (FP6 IP #27648) and partially by the projects UNiSIX (Marie-Curie #509595), I-Cores (IRG #224759) and the HiPEAC Network  ... 
doi:10.1109/mm.2010.77 fatcat:jzsphc2sqrgpfh6rxdgvuswv5y

An Adaptive Message Passing MPSoC Framework

Gabriel Marchesan Almeida, Gilles Sassatelli, Pascal Benoit, Nicolas Saint-Jean, Sameer Varyani, Lionel Torres, Michel Robert
2009 International Journal of Reconfigurable Computing  
load balancing and task migration.  ...  The work presented in this paper relies on a homogeneous NoC-based MPSoC framework we developed for exploring scalable and adaptive on-line continuous mapping techniques.  ...  The system is based on an array of compact general-purpose PEs interconnected through a packet switching Network-on-Chip.  ... 
doi:10.1155/2009/242981 fatcat:rfuqczbc7fcgbnetauq4ba7y5i

High-Performance Energy-Efficient Multicore Embedded Computing

A. Munir, S. Ranka, A. Gordon-Ross
2012 IEEE Transactions on Parallel and Distributed Systems  
With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multicore to exploit this high-transistor density for high performance.  ...  The increase in on-chip transistor density exacerbates power/thermal issues in embedded systems, which necessitates novel hardware/software power/thermal management techniques to meet the ever-increasing  ...  HPEEC software-based techniques include data forwarding, task scheduling, task migration, and load balancing.  ... 
doi:10.1109/tpds.2011.214 fatcat:vagqmojdsjevvc2u2ewqrcjjpq

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip

Weichen Liu, Xuan Wang, Jiang Xu, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang
2014 ACM Journal on Emerging Technologies in Computing Systems  
On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.  ...  A hardware-software collaborative approach is proposed to solve soft error problems: a hardware-based on-chip sensor network is built for soft error detection, and a software-based recovery mechanism is  ...  Sensor Network-on-Chip (SENoC) is a pervasive solution to chip monitoring and management, where on-chip sensors form a network for detection, communication, and management in order to keep the chip correct  ... 
doi:10.1145/2564928 fatcat:66r4x436rfh2jhx7olz6tbcrqy

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Weichen Liu, Yu Wang, Xuan Wang, Jiang Xu, Huazhong Yang
2013 IEEE Transactions on Parallel and Distributed Systems  
In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC.  ...  Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system on chip (MPSoC) to satisfy the increasing demands of applications.  ...  In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC.  ... 
doi:10.1109/tpds.2012.193 fatcat:ewyt5up7b5bb3cccxhdhhchwuu

ROAdNoC: Runtime observability for an adaptive network on chip architecture

Mohammad Abdullah Al Faruque, Thomas Ebi, Jorg Henkel
2008 2008 IEEE/ACM International Conference on Computer-Aided Design  
Hard-to-predict system behavior and/or reliability issues resulting from migrating to new technology nodes requires considering runtime adaptivity in future on-chip systems.  ...  We are presenting the first comprehensive runtime observability infrastructure for an adaptive network on chip architecture which is flexible (e.g. in choosing the routing path), hardly intrusive, and  ...  INTRODUCTION AND MOTIVATION The 100 Billion transistor chip is predicted to emerge within a decade [3] .  ... 
doi:10.1109/iccad.2008.4681628 dblp:conf/iccad/FaruqueEH08 fatcat:7tdkuaosubho7c746d5kn2gkni

Efficient data streaming with on-chip accelerators: Opportunities and challenges

Rui Hou, Lixin Zhang, Michael C. Huang, Kun Wang, Hubertus Franke, Yi Ge, Xiaotao Chang
2011 2011 IEEE 17th International Symposium on High Performance Computer Architecture  
Thus, on-chip accelerator architectures deserve more attention from the research community. There is a wide spectrum of research opportunities for design and optimization of accelerators.  ...  This paper attempts to bring out some insights by studying the data access streams of on-chip accelerators that hopefully foster some future research in this area.  ...  We would also like to thank Yu Zhang from IBM China Research Lab, and Jian Li from IBM Austin Research Lab, for the technical discussions and valuable comments on earlier stages of this work.  ... 
doi:10.1109/hpca.2011.5749739 dblp:conf/hpca/HouZHWFGC11 fatcat:xecaxvszjbbcxgvqtlfrfcb2ma

Runtime QoS Support for MPSoC

Marcelo Ruaro, Everton A. Carara, Fernando G. Moraes
2014 Proceedings of the 27th Symposium on Integrated Circuits and Systems Design - SBCCI '14  
The main goal of the present work is to employ a low overhead task migration combined with task scheduling priority, to increase the computation resources for RT applications.  ...  The proposed work provides a runtime support for QoS acting in the PEs, coupled to a monitoring scheme at the task level.  ...  We define the reaction time as the time between the start of the BE interference and the triggering of the adaptation.  ... 
doi:10.1145/2660540.2661011 dblp:conf/sbcci/RuaroCM14 fatcat:lhxxgzibcrgexl5m4lg4galzqy
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