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POSTER: A Collaborative Multi-Factor Scheduler for Asymmetric Multicore Processors

Teng Yu, Pavlos Petoumenos, Vladimir Janjic, Mingcan Zhu, Hugh Leather, John Thomson
2019 2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT)  
Asymmetric multicore processors (AMP) are necessary for extracting performance in an era of limited power budget and dark silicon.  ...  We have efficient symmetric schedulers, efficient asymmetric schedulers for single-threaded workloads, and efficient asymmetric schedulers for single program workloads.  ...  Among heterogeneous systems, single-ISA asymmetric multicore processors (AMPs) are becoming increasingly popular.  ... 
doi:10.1109/pact.2019.00058 dblp:conf/IEEEpact/YuPJZLT19 fatcat:omytvlwduvhnpfifystzkfts4q

ATIP/A*CRC Workshop on Accelerator Technologies for High-Performance Computing: Does Asia Lead the Way? Programme Handbook [article]

Michalewicz Marek, Kahaner David
2012 Zenodo  
We hope this will provide a good opportunity, especially for our foreign visitors, to learn about some of the research work conducted locally and explore potential collaborations.  ...  We believe everyone will have a fruitful workshop and we thank you for participating.  ...  I will present OIST's existing data infrastructure and show new performance results for various file system options on this and newer hardware.  ... 
doi:10.5281/zenodo.3977457 fatcat:v2aftckqinasxk5ugdw27vinpa

Processing Panorama Video in Real-time

Håkon Kvale Stensland, Vamsidhar Reddy Gaddam, Marius Tennøe, Espen Helgedagsrud, Mikkel Næss, Henrik Kjus Alstad, Carsten Griwodz, Pål Halvorsen, Dag Johansen
2014 International Journal of Semantic Computing (IJSC)  
This shift introduced a new challenge for programmers: Legacy applications, written without parallelization in mind, gain no benefits from moving to multicore and heterogeneous architectures.  ...  For a very long time, one of the important means of increasing performance was to increase the clock frequency.  ...  x86 Processor Architecture The x86 processors in modern computers are a symmetric multicore CPU with a shared memory model.  ... 
doi:10.1142/s1793351x14400054 fatcat:hafewx3ekrcfpat2osb67fjugi

Automatic Generation of Timing Models for Timing Analysis of High-Level Code

Peter Altenbernd, Andreas Ermedahl, Björn Lisper, Jan Gustafsson
2011 International Conference on Real-Time and Network Systems  
In this paper, we present an optimal k-exclusion locking protocol for globally-scheduled job-level static-priority (JLSP) systems.  ...  Graphics processing units (GPUs) are becoming increasingly important in today's platforms as their increased generality allows for them to be used as powerful co-processors.  ...  ACKNOWLEDGMENTS We would like to thank Alejandro Masrur for his useful comments on a preliminary version of this paper and Jai Dhariwal for proofreading.  ... 
dblp:conf/rtns/AltenberndELG11 fatcat:gh4qe3npgfg4ncejm53oqo75py

Heterogeneity-aware scheduling and data partitioning for system performance acceleration

Teng Yu, John Donald Thomson
2020
It covers a wide variety of systems, including an OS scheduler targeting on-chip asymmetric multi-core processors (AMPs) on mobile devices, a hierarchical many-core supercomputer and multi-FPGA systems  ...  partitioning method for a modern supercomputer, and a topological-ranking heuristic based schedule for a multi-FPGA based reconfigurable cluster.  ...  COLAB: A Heterogeneity-Aware Scheduler for Asymmetric Chip Multi-core Processors two main functions are listed below: Algorithm 1 Collaborative Multi-factor Scheduler targeting Asymmetric Multicore Processors  ... 
doi:10.17630/10023-19797 fatcat:beawpn7pvbe6hfiajl5b5n37ee

Parallel Programming With Global Asynchronous Memory: Models, C++ Apis And Implementations

Maurizio Drocco, Marco Aldinucci
2017 Zenodo  
On top of smart pointers, we propose a high-level C++ template library for writing applications in terms of dataflow-like networks, namely GAM nets, consisting of stateful processors exchanging pointers  ...  We advocate an alternative programming model for distributed computing based on a Global Asynchronous Memory (GAM), aiming to avoid coherency and consistency problems rather than solving them.  ...  • The farm scheduler is mapped to a source processor (S); • Each farm worker is mapped to a filter processor (W); • The farm collector is mapped to a sink processor (C).  ... 
doi:10.5281/zenodo.1037585 fatcat:ecjm5xj5x5exbfxe3eokl7uneu

Implementation of Fog computing for reliable E-health applications

Razvan Craciunescu, Albena Mihovska, Mihail Mihaylov, Sofoklis Kyriazakos, Ramjee Prasad, Simona Halunga
2015 2015 49th Asilomar Conference on Signals, Systems and Computers  
The final evaluation is done with computer simulation of a multi-cell system.  ...  Specifically, we introduce a concept for sparse joint activity, channel and data detection in the context of the Coded ALOHA (FDMA) protocol.  ...  a 2D mesh of 164 programmable processors designed for general DSP applications.  ... 
doi:10.1109/acssc.2015.7421170 dblp:conf/acssc/CraciunescuMMKP15 fatcat:qm6mki5z6bcvrfimkmqjyrxaxm

Ping-pong beam training for reciprocal channels with delay spread

Elisabeth de Carvalho, Jorgen Bach Andersen
2015 2015 49th Asilomar Conference on Signals, Systems and Computers  
Its purpose is threefold: (1) Determine the suitability of processor arrays for this kind of application. (2) Develop a runtime software infrastructure that supports streaming applications on processor  ...  This paper reports on a case study in which an at-size application is ported onto a commercially available processor array.  ...  , which contains a 2D mesh of 164 programmable processors designed for general DSP applications.  ... 
doi:10.1109/acssc.2015.7421451 dblp:conf/acssc/CarvalhoA15 fatcat:mqokuvnh3zg45licnfbgxyvxfu

Design of large polyphase filters in the Quadratic Residue Number System

Gian Carlo Cardarilli, Alberto Nannarelli, Yann Oster, Massimo Petricca, Marco Re
2010 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers  
FPXAs can also be mapped onto multicore processors for flexible emulation.  ...  When the cooperation between the cells is asymmetric, we show that the optimal scheduling policy has a greedy flavor and is simple to implement.  ... 
doi:10.1109/acssc.2010.5757589 fatcat:ccxnu5owr5fyrcjcqukumerueq

The perceptual flow of phonetic feature processing

Steven Greenberg, Thomas Ulrich Christiansen
2008 Journal of the Acoustical Society of America  
See poster sessions for topics and abstracts.  ...  for presentation of poster papers on various topics in acoustics.  ...  Finally, we address the implementation of the technique for non-destructive Evaluation ͑NDE͒ real-world applications using multi-threaded computational codes to be run on common multicore desktop computers  ... 
doi:10.1121/1.2935993 fatcat:l2ix2ph575gh7l27xtjq264qkm

Amplitude modulation depth discrimination in hearing‐impaired and normal‐hearing listeners

Stephan D. Ewert, Jutta Volmer, Torsten Dau, Jesko Verhey
2008 Journal of the Acoustical Society of America  
See poster sessions for topics and abstracts.  ...  for presentation of poster papers on various topics in acoustics.  ...  Finally, we address the implementation of the technique for non-destructive Evaluation ͑NDE͒ real-world applications using multi-threaded computational codes to be run on common multicore desktop computers  ... 
doi:10.1121/1.2935715 fatcat:qsqohnv63fdsjgegqb2h5s7r7q

Cross‐spectral synergy and consonant identification

Thomas Ulrich Christiansen, Steven Greenberg
2008 Journal of the Acoustical Society of America  
See poster sessions for topics and abstracts.  ...  for presentation of poster papers on various topics in acoustics.  ...  Finally, we address the implementation of the technique for non-destructive Evaluation ͑NDE͒ real-world applications using multi-threaded computational codes to be run on common multicore desktop computers  ... 
doi:10.1121/1.2935680 fatcat:znwocm35unasharfwbcap5omim

GHEVC: An Efficient HEVC Decoder for Graphics Processing Units

Diego F. de Souza, Aleksandar Ilic, Nuno Roma, Leonel Sousa
2017 IEEE transactions on multimedia  
Such an increased burden is a limiting factor to accomplish realtime decoding, specially for high definition video sequences (e.g., Ultra HD 4K).  ...  In this scenario, a highly parallel HEVC decoder for the state-of-the-art graphics processor units (GPUs) is presented, i.e., GHEVC.  ...  Although the operations within a single Stream are launched in order by the CPU, they may be scheduled out of order across different Streams.  ... 
doi:10.1109/tmm.2016.2625261 fatcat:jdjab7n6ibcvfig3n45f5ojca4

A virtual auditory environment for investigating the auditory signal processing of realistic sounds

Sylvain Favrot, Jörg M. Buchholz
2008 Journal of the Acoustical Society of America  
Finally, we address the implementation of the technique for non-destructive Evaluation ͑NDE͒ real-world applications using multi-threaded computational codes to be run on common multicore desktop computers  ...  This poster illustrates the importance of these factors to perception.  ...  Even with the emergence of novel multicore processors, leading providers ͑e.g., Mercury Computers͒ still include explicit corner turning stages in their computational flow architectures for multidimensional  ... 
doi:10.1121/1.2936003 fatcat:ontu6yamdvgbnooet5fe36fm74

Analysis of room transfer function and reverberant signal statistics

Eleftheria Georganti, John Mourjopoulos, Finn Jacobsen
2008 Journal of the Acoustical Society of America  
Finally, we address the implementation of the technique for non-destructive Evaluation ͑NDE͒ real-world applications using multi-threaded computational codes to be run on common multicore desktop computers  ...  This poster illustrates the importance of these factors to perception.  ...  Even with the emergence of novel multicore processors, leading providers ͑e.g., Mercury Computers͒ still include explicit corner turning stages in their computational flow architectures for multidimensional  ... 
doi:10.1121/1.2935346 fatcat:lxgnqr6tozajhge3ydet3xomam
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