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P systems based computing polynomials: design and formal verification

Weitao Yuan, Gexiang Zhang, Mario J. Pérez-Jiménez, Tao Wang, Zhiwei Huang
2016 Natural Computing  
We also discuss the descriptive computational resources required by the designed k-order polynomial P system.  ...  Automatic design of P systems is an attractive research topic in the community of membrane computing.  ...  Wang and Z. Huang is supported by the National Natural Science Foundation of China (61170016, 61373047). The work of M.J.  ... 
doi:10.1007/s11047-016-9577-y fatcat:w27ugxmalvc2tpt5zogac3lhqi

Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials

Akira Ito, Rei Ueno, Naofumi Homma
2021 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., the specification of a GF arithmetic circuit) can be represented as polynomials over F2, the proposed method formally checks the equivalence between GF polynomials derived from a netlist and the specification  ...  We demonstrated the efficiency and effectiveness of the proposed method via a set of experimental verifications.  ...  We start computing polynomials from the PIs and finally calculate all polynomials p 1 , p 2 , . . . , p l , including those of the POs.  ... 
doi:10.1109/tcad.2021.3059924 fatcat:x43rqximubcylmcsorhnpmnjyu

Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs

Mohamed H. Zaki, Ghiath Al-Sammane, Sofi`ene Tahar, Guy Bois
2007 Formal Methods in Computer Aided Design (FMCAD'07)  
Recently, several formal techniques have been introduced for AMS verification. In this paper, we propose a difference equations based bounded model checking approach for AMS systems.  ...  We illustrate our approach on the verification of several AMS designs including ∆Σ modulator and oscillator circuits.  ...  Boosted by previous successes in the verification of corner cases in digital designs, formal methods became a serious candidate for the verification of AMS systems.  ... 
doi:10.1109/fmcad.2007.4402002 fatcat:ztny2yra6rcfhd35tmlo377jaa

Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs

Mohamed H. Zaki, Ghiath Al-Sammane, Sofi`ene Tahar, Guy Bois
2007 Formal Methods in Computer Aided Design (FMCAD'07)  
Recently, several formal techniques have been introduced for AMS verification. In this paper, we propose a difference equations based bounded model checking approach for AMS systems.  ...  We illustrate our approach on the verification of several AMS designs including ∆Σ modulator and oscillator circuits.  ...  Boosted by previous successes in the verification of corner cases in digital designs, formal methods became a serious candidate for the verification of AMS systems.  ... 
doi:10.1109/famcad.2007.25 dblp:conf/fmcad/ZakiATB07 fatcat:xfwaagggfnc7pilohqaw4pcc6y

Integrating Abstraction Techniques for Formal Verification of Analog Designs

Mohamed H. Zaki, William Denman, Sofiène Tahar, Guy Bois
2009 Journal of Aerospace Computing Information and Communication  
Verification is applied based on combining techniques from constraint solving and computer algebra along with symbolic model checking.  ...  The verification of analog designs is a challenging and exhaustive task that requires deep understanding of physical behaviours.  ...  On the contrary, we benefit from advances in formal verification of analog designs to propose a novel verification framework for analog designs modeled using bond graphs. Analog design verification.  ... 
doi:10.2514/1.44289 fatcat:xdzng7d4knfjxnjkzg6l5t7j6i

Interrupt Timed Automata: verification and expressiveness

Béatrice Bérard, Serge Haddad, Mathieu Sassolas
2012 Formal methods in system design  
In the next step, we investigate the verification of real time properties over ITA. We prove that model checking SCL, a fragment of a timed linear time logic, is undecidable.  ...  We introduce the class of Interrupt Timed Automata (ITA), a subclass of hybrid automata well suited to the description of timed multi-task systems with interruptions in a single processor environment.  ...  This work was supported by projects DOTS (ANR-06-SETI-003, French government), IMPRO (ANR-2010-BLAN-0317, French government) and COCHAT (Digiteo 2009-27HD, Région Île de France).  ... 
doi:10.1007/s10703-011-0140-2 fatcat:smfbvlvkajdjnjyvuhanfpq7ou

The ins and outs of first-order runtime verification

Andreas Bauer, Jan-Christoph Küster, Gil Vegliach
2015 Formal methods in system design  
The main purpose of this paper is to introduce a first-order temporal logic, LTL FO , and a corresponding monitor construction based on a new type of automaton, called spawning automaton.  ...  The automata-based monitor construction for LTL FO is given in §5 along with two comprehensive examples to convey an intuitive understanding of the underlying principles and ideas.  ...  NICTA is funded by the Australian Government as represented by the Department of Broadband, Communications and the Digital Economy and the Australian Research Council through the ICT Centre of Excellence  ... 
doi:10.1007/s10703-015-0227-2 fatcat:7o6uwx5gwje27aaf276ityc6oa

Automated verification of automata communicating via FIFO and bag buffers

Lakhdar Akroun, Gwen Salaün
2017 Formal methods in system design  
This enables one to check temporal properties on the system for that bound and this ensures that the system will preserve them whatever larger bounds are used for buffers.  ...  This article presents new results for the automated verification of automata communicating asynchronously via FIFO or bag buffers.  ...  For instance, they prove that a symbolic representation of the reachability set is computable in polynomial time and show how to use this result to solve several verification problems.  ... 
doi:10.1007/s10703-017-0285-8 fatcat:jg5ktxpj2rc5vlcjbhcp4afgky

A Review Report on Multi-Voltage Rule Check and Formal Verification of ASIC Design

M. Mythili, Sujata D Badiger, Jayati Singh, Venkata Rangam Totakura
2020 Zenodo  
It provides a detailed review of both formal verification and multi-voltage rule check.  ...  So Formal Verification is performed to confirm that Golden netlist (Reference) and revised netlist are equivalent at different phases, example Synthesis, Design for Testability (DFT), Place and route.  ...  Formal Pro Formal verification (FV) is another process used to perform the equivalence check between two netlists at different stage in ASIC design flow.  ... 
doi:10.5281/zenodo.3890998 fatcat:57roby3725by5gj2gk56nquede

An approach for the formal verification of DSP designs using Theorem proving

B. Akbarpour, S. Tahar
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper proposes a framework for the incorporation of formal methods in the design flow of digital signal processing (DSP) systems in a rigorous way.  ...  This framework enables the formal verification of DSP designs that in the past could only be done partially using conventional simulation techniques.  ...  This paper is an extended and more generic version of an earlier publication in Formal Methods in Computer-Aided Design (FMCAD 2004) on FFT verification [2] .  ... 
doi:10.1109/tcad.2005.857314 fatcat:os73cqrturglnis2jv2gcub6mi

Efficient Verification of Sequential and Concurrent C Programs

S. Chaki, E. Clarke, A. Groce, J. Ouaknine, O. Strichman, K. Yorav
2004 Formal methods in system design  
However, the state-space explosion problem in model checking remains the chief obstacle to the practical verification of real-world distributed systems.  ...  Additionally, a key feature of our approach is that if a property can be proved to hold or not hold based on a given finite set of predicates P, the predicate refinement procedure we propose in this article  ...  Acknowledgements We thank Rupak Majumdar and Ranjit Jhala for their help with blast.  ... 
doi:10.1023/b:form.0000040026.56959.91 fatcat:cd4xubqj4zgmnfqe43bdnv7cxi

Formal Design and Verification of Long-Running Transactions with Extensible Coordination Tools

Natallia Kokash, Farhad Arbab
2013 IEEE Transactions on Services Computing  
Our solution is based on the channel-based coordination language Reo, which is an expressive, compositional, and semantically precise design language admitting formal reasoning.  ...  Ensuring transactional behavior of business processes and web service compositions is an essential issue in the area of service-oriented computing.  ...  their formal verification.  ... 
doi:10.1109/tsc.2011.46 fatcat:v5uwfpb2ajajvfciyxtojdry6m

Efficient verification of periodic programs using sequential consistency and snapshots

Sagar Chaki, Arie Gurfinkel, Nishant Sinha
2014 2014 Formal Methods in Computer-Aided Design (FMCAD)  
We develop an approach based on generating, and solving, a provably correct verification condition (VC).  ...  We verify safety properties of periodic programs, consisting of periodically activated threads scheduled preemptively based on their priorities.  ...  ACKNOWLEDGMENT Copyright 2014 Carnegie Mellon University and FMCAD, Inc. 2  ... 
doi:10.1109/fmcad.2014.6987595 dblp:conf/fmcad/ChakiGS14 fatcat:3xjfmzn4i5grpfsbo6ad5l7zam

Formal verification of memory circuits by switch-level simulation

R.E. Bryant
1991 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This approach to verification is fast, requires minimal attention on the part of the user to the circuit details, and can utilize more sophisticated circuit models than other approaches to formal verification  ...  The technique has been applied to a CMOS static RAM design using the COSMOS switch-level simulator.  ...  Limitations of Formal Verification Formal verification involves proving that, under some abstract model of operation, the system will behave as specified for all possible input sequences.  ... 
doi:10.1109/43.62795 fatcat:5vxetwivnjbwxazyexqfes3jpa

Lattice-based SMT for program verification

Karine Even-Mendoza, Antti E. J. Hyvärinen, Hana Chockler, Natasha Sharygina
2019 Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design - MEMOCODE '19  
We present a lattice-based satisfiability modulo theory for verification of programs with library functions, for which the mathematical libraries supporting these functions contain a high number of equations  ...  and inequalities.  ...  SMT-based bounded model checking Let P be a loop-free program represented as a transition system, and t a safety property, that is, a formula over the variables of P .  ... 
doi:10.1145/3359986.3361214 dblp:conf/memocode/Even-MendozaHCS19 fatcat:tgyvmy6pgncdha7rhrdvjpb46e
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