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Out-of-order execution may not be cost-effective on processors featuring simultaneous multithreading

S. Hily, A. Seznec
1999 Proceedings Fifth International Symposium on High-Performance Computer Architecture  
80% 90% 100% in-order out-of-order ratio 0IPELINE "RANCH #ACHES 0 1 2 3 4 5 6 7 8 1 thread 2 threads 4 threads ¡ ¢£ ¤ ¢ ¥ ¦ § 0% 10% 20% 30%  ...  100% in-order out-of-order ratio 0IPELINE #ACHES 0 1 2 3 4 5 6 7 8 1 thread 2 threads 4 threads ¡ ¢£ ¤ ¢ ¥ ¦ § 0% 10% 20% 30% 40% 50% 60% 70%  ... 
doi:10.1109/hpca.1999.744331 dblp:conf/hpca/HilyS99 fatcat:q3a7z4lavvedlfgt4l5k52r2jq

Multithreaded Processors

T. Ungerer
2002 Computer journal  
Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple  ...  The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip.  ...  The processor proposal features out-of-order execution, a large on-chip L2 cache, a direct RAMBUS interface and an on-chip router for system interconnect of a directory based, cache-coherent non-uniform  ... 
doi:10.1093/comjnl/45.3.320 fatcat:hlkkabuhrzhkrmuyqomzfmc6zm

Multi-Threaded Processors [chapter]

David Padua, Amol Ghoting, John A. Gunnels, Mark S. Squillante, José Meseguer, James H. Cownie, Duncan Roweth, Sarita V. Adve, Hans J. Boehm, Sally A. McKee, Robert W. Wisniewski, George Karypis (+29 others)
2011 Encyclopedia of Parallel Computing  
Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple  ...  The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip.  ...  The processor proposal features out-of-order execution, a large on-chip L2 cache, a direct RAMBUS interface and an on-chip router for system interconnect of a directory based, cache-coherent non-uniform  ... 
doi:10.1007/978-0-387-09766-4_423 fatcat:heb3n2cfwnbi5nvxv5kvxd2xgm

Multithreading decoupled architectures for complexity-effective general purpose computing

Michael Sung, Ronny Krashinsky, Krste Asanović
2001 SIGARCH Computer Architecture News  
A proposal for a multithreaded decoupled control/access/execute architecture is presented as a platform for achieving high performance on general purpose workloads.  ...  It is argued that such a decoupled architecture is more complexity-effective and scalable than comparable superscalar processors, which incorporate enormous amounts of complexity for modest performance  ...  used by out-of-order superscalars).  ... 
doi:10.1145/563647.563658 fatcat:fjmdpove5ravhclvctbfurz6im

Improving latency tolerance of multithreading through decoupling

J.-M. Parcerisa, A. Gonzalez
2001 IEEE transactions on computers  
Since decoupling features an excellent memory latency hiding efficiency, the large amount of parallelism exploited by multithreading may be used to hide the latency of functional units and keep them fully  ...  This work presents and evaluates a novel processor microarchitecture which combines two paradigms: simultaneous multithreading and access/execute decoupling.  ...  This work has been supported by the Ministry of Education of Spain under contract CYCIT TIC98-0511 and by the European Union through the ESPRIT program under the MHAOTEU (EP24942) project.  ... 
doi:10.1109/12.956093 fatcat:id5zuvaajfcildot55nuokrb4m

A survey of processors with explicit multithreading

Theo Ungerer, Borut Robič, Jurij Šilc
2003 ACM Computing Surveys  
Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple  ...  The contexts of two or more threads of control are often stored in separate on-chip register sets.  ...  The processor proposal featured out-of-order execution, a large on-chip secondary cache, a direct RAMBUS interface, and an on-chip router for system interconnect of a directory based, cache-coherent NUMA  ... 
doi:10.1145/641865.641867 fatcat:u6x7jdmkfvexnm3culskjsoxwi

Timed Petri Nets in Performance Exploration of Simultaneous Multithreading [chapter]

Wlodek M.
2012 Petri Nets - Manufacturing and Computer Science  
Zuberek Memorial University, St.John's, Canada, University of Life Sciences, Warsaw, Poland  ...  Acknowledgement The Natural Sciences and Engineering Research Council of Canada partially supported this research through grant RGPIN-8222. Author details Wlodek M.  ...  The main objective of this work is to study the performance of simultaneously multithreaded processors in order to determine how effective simultaneous multithreading can be.  ... 
doi:10.5772/48601 fatcat:tf4cywuxz5dx7lih22fkxuskxq

The synergy of multithreading and access/execute decoupling

J.-M. Parcerisa, A. Gonzalez
1999 Proceedings Fifth International Symposium on High-Performance Computer Architecture  
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading.  ...  Its partitioned layout, together with its in-order issue policy makes it potentially less complex, in terms of critical path delays, than a centralized out-of-order design, to support future growths in  ...  It may be argued that in-order processors have a limited potential to exploit ILP.  ... 
doi:10.1109/hpca.1999.744329 dblp:conf/hpca/ParcerisaG99 fatcat:g35wkgnv2jatxpiio3s7kwxq2u

A multithreaded PowerPC processor for commercial servers

J. M. Borkenhagen, R. J. Eickemeyer, R. N. Kalla, S. R. Kunkel
2000 IBM Journal of Research and Development  
of execution time that is wasted on cache misses.  ...  A multithreaded PowerPC processor for commercial servers This paper describes the microarchitecture of the RS64 IV, a multithreaded PowerPC ® processor, and its memory system.  ...  In an out-of-order processor, simultaneous multithreading would be the natural choice.  ... 
doi:10.1147/rd.446.0885 fatcat:6n35k2rsqvbpvigzujaizluw5a

Fine-grain multithreading with the EM-X multiprocessor

Andrew Sohn, Yuetsu Kodama, Jui Ku, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
1997 Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures - SPAA '97  
Even in the absence of thread computation parallelism, multithreading helps overlap over 3570 of the communication time for bitonic sorting.  ...  This report explicates the multithreading capabilities of the EM-X distributed-memory multiprocessor through empirical studies.  ...  Sorting is implemented in such a way that a processor may or may not have to read all the elements from the mate processor.  ... 
doi:10.1145/258492.258511 dblp:conf/spaa/SohnKKSSYSY97 fatcat:yxikd7vw5vezrdvo7vwiozgjrq

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1998 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98  
WC also show that simultaneous multithreading is an attractive alternative to single-chip multiprocessors; simultaneous multithreaded processors with a variety of organizations outperform comiponding conventional  ...  We present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor. and single-chip, multiple-issue multiprocessing  ...  We would also like to thank Burton Smith, Norm Jouppi, and the reviewers for helpful comments and suggestions on the paper and the research.  ... 
doi:10.1145/285930.286011 dblp:conf/isca/TullsenEL98a fatcat:wzwmqqcnj5bz3faupjps7d6tay

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1995 Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95  
We also show that simultaneous multithreading is an attractive alternative to single-chip multiprocessors; simultaneous multithreaded processors with a variety of organizations outperform corresponding  ...  We present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing  ...  We would also like to thank Burton Smith, Norm Jouppi, and the reviewers for helpful comments and suggestions on the paper and the research.  ... 
doi:10.1145/223982.224449 dblp:conf/isca/TullsenEL95 fatcat:rj3illxasbalhkiz4ygcsjsvdi

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1995 SIGARCH Computer Architecture News  
We also show that simultaneous multithreading is an attractive alternative to single-chip multiprocessors; simultaneous multithreaded processors with a variety of organizations outperform corresponding  ...  We present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing  ...  We would also like to thank Burton Smith, Norm Jouppi, and the reviewers for helpful comments and suggestions on the paper and the research.  ... 
doi:10.1145/225830.224449 fatcat:gtheubj4tbcqxokcmbrfoihxym

Simultaneous multithreading: a platform for next-generation processors

S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, R.L. Stamm, D.M. Tullsen
1997 IEEE Micro  
We also thank Jennifer Anderson of DEC Western Research Laboratory for copies of the SpecFP95 benchmarks, parallelized by the most recent version of the SUIF compiler, and Sujay Parekh for comments on  ...  Acknowledgments We thank John O'Donnell of Equator Technologies, Inc. and Tryggve Fossum of Digital Equipment Corp. for the source to the Alpha AXP version of the Multiflow compiler.  ...  and out-of-order execution hardware.  ... 
doi:10.1109/40.621209 fatcat:zmx4yx2flnfazi3b6zdwhavnam

Trends in Processor Architecture [article]

Antonio Gonzalez
2018 arXiv   pre-print
It starts with an analysis of the past evolution of processors and the main driving forces behind it, and then it focuses on a description of the main architectural features of current processors.  ...  Finally, it presents a discussion on some promising directions for future evolution of processor architectures.  ...  Instead of stalling all instructions younger than this consumer, as in-order processors do, out-of-order processors can execute younger instructions, provided that they do not depend on the load.  ... 
arXiv:1801.05215v1 fatcat:wh3og7wn4jcp3izqojc3hmalxa
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