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Optimizing for space and time usage with speculative partial redundancy elimination

Bernhard Scholz, Nigel Horspool, Jens Knoop
2004 SIGPLAN notices  
Speculative partial redundancy elimination (SPRE) uses execution profiles to improve the expected performance of programs.  ...  One surprising result that an explosion in size may occur if speed is the sole goal, and consideration of space usage is therefore important.  ...  ACKNOWLEDGMENTS We would like to thank Erik Eckstein who had the original idea for the local transformation of a basic block.  ... 
doi:10.1145/998300.997195 fatcat:i4tzwcpclrgp3hiiugzyjyumdu

Optimizing for space and time usage with speculative partial redundancy elimination

Bernhard Scholz, Nigel Horspool, Jens Knoop
2004 Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '04  
Speculative partial redundancy elimination (SPRE) uses execution profiles to improve the expected performance of programs.  ...  One surprising result that an explosion in size may occur if speed is the sole goal, and consideration of space usage is therefore important.  ...  ACKNOWLEDGMENTS We would like to thank Erik Eckstein who had the original idea for the local transformation of a basic block.  ... 
doi:10.1145/997163.997195 dblp:conf/lctrts/ScholzHK04 fatcat:i3wpez5vg5fw7g553ig52jyhui

Hardware atomicity for reliable software speculation

Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig Zilles
2007 SIGARCH Computer Architecture News  
Its incorporation creates new opportunities for existing optimization passes, as well as greatly simplifying the implementation of additional optimizations (e.g., partial inlining, partial loop unrolling  ...  , and speculative lock elision).  ...  Srinivasan, and Yury Yudin for their technical support and feedback relating to this project.  ... 
doi:10.1145/1273440.1250684 fatcat:nmvor2fagna3vp3bksps32zwni

Hardware atomicity for reliable software speculation

Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig Zilles
2007 Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07  
Its incorporation creates new opportunities for existing optimization passes, as well as greatly simplifying the implementation of additional optimizations (e.g., partial inlining, partial loop unrolling  ...  , and speculative lock elision).  ...  Srinivasan, and Yury Yudin for their technical support and feedback relating to this project.  ... 
doi:10.1145/1250662.1250684 dblp:conf/isca/NeelakantamRSSZ07 fatcat:bbeexcpx4zhaxnmuo2twhajria

The Blue Gene/Q Compute chip

Ruud Haring
2011 2011 IEEE Hot Chips 23 Symposium (HCS)  
packaging  floor space efficiency -Reliability • Long MTBF for large installations Chip design objectives:  optimize FLOPS/Watt  optimize redundancy / ECC usage / SER sensitivity BlueGene  ...  " of user-defined transactions • eliminates need for locks • load/store conflicts detected and reported --software will need to resolve Speculative Execution: • allows coarse grain multi-threading for  ...  The development, release, and timing of any future features or functionality described for our products remains at our sole discretion.  ... 
doi:10.1109/hotchips.2011.7477488 fatcat:nhwlkj3x2zfwjngllgct55plta

Low-Power/Energy Compiler Optimizations [chapter]

Ulrich Kremer
2005 Low-Power Processors and Systems on Chips  
Each of these devices has their own requirements for performance, power dissipation, and energy usage, and typically implements a particular tradeoff among these entities.  ...  Allowing components of these devices to be controlled by software has opened up opportunities for compilation and operating strategies to reduce power dissipation and energy usage, at the potential cost  ...  Acknowledgement This work has been partially supported by NSF CAREER award #9985050.  ... 
doi:10.1201/9781420037203.ch18 fatcat:iuy354t3fbe2tcne6nxzez3pfm

Low- Power/ Energy Compiler Optimizations [chapter]

Ulrich Kremer
2004 Computer Engineering Series  
Each of these devices has their own requirements for performance, power dissipation, and energy usage, and typically implements a particular tradeoff among these entities.  ...  Allowing components of these devices to be controlled by software has opened up opportunities for compilation and operating strategies to reduce power dissipation and energy usage, at the potential cost  ...  Acknowledgement This work has been partially supported by NSF CAREER award #9985050.  ... 
doi:10.1201/9781420039559.ch35 fatcat:dz3oj3vthbea3nekjmvvxqzc5y

A lifetime optimal algorithm for speculative PRE

Jingling Xue, Qiong Cai
2006 ACM Transactions on Architecture and Code Optimization (TACO)  
Our results show that MC-PRE (or MC-PRE comp ) is capable of eliminating more partial redundancies than both LCM and CMP-PRE (especially in functions with complex control flow), and, in addition, MC-PRE  ...  A lifetime optimal algorithm, called MC-PRE, is presented for the first time that performs speculative PRE based on edge profiles.  ...  ACKNOWLEDGMENTS We wish to thank the reviewers and editors for their helpful comments and suggestions. This work is partially supported by an ARC grant DP0452623.  ... 
doi:10.1145/1138035.1138036 fatcat:6jxnqgxw6vbzpoefpqlt56pacm

DAFT: Decoupled Acyclic Fault Tolerance

Yun Zhang, Jae W. Lee, Nick P. Johnson, David I. August
2011 International journal of parallel programming  
Redundant hardware modules can detect such faults, but software techniques are more appealing for their low cost and flexibility.  ...  Where possible, values are speculated to be correct and only communicated to the redundant thread at essential program points.  ...  This is not redundant code and cannot be removed through dead code elimination.  ... 
doi:10.1007/s10766-011-0183-4 fatcat:5sfdnspbtbbsbcizffokwtvcv4

DAFT

Yun Zhang, Jae W. Lee, Nick P. Johnson, David I. August
2010 Proceedings of the 19th international conference on Parallel architectures and compilation techniques - PACT '10  
Redundant hardware modules can detect such faults, but software techniques are more appealing for their low cost and flexibility.  ...  Where possible, values are speculated to be correct and only communicated to the redundant thread at essential program points.  ...  This is not redundant code and cannot be removed through dead code elimination.  ... 
doi:10.1145/1854273.1854289 dblp:conf/IEEEpact/ZhangLJA10 fatcat:4ktoevsdzbd4tkj6bgzoyktad4

Performance analysis of Low energy and highspeed DA-RNS based FIR filter design for SDR Applications on FPGA

B. N. Mohan Kumar, H. G. Rangaraju
2021 North atlantic university union: International Journal of Circuits, Systems and Signal Processing  
The proposed FIR filter with core optimized RNS has the benefit of lowering processing latency delay while rising performance torque.  ...  Through RNS replication, accompanied by conditional delay optimized reverse processing to minimize the FIR filter trade-off features with filter duration optimized Residue Number System arithmetic is proposed  ...  Defined Radio application with high speed and low energy usage.  ... 
doi:10.46300/9106.2021.15.78 fatcat:4mwiwfawxngcdote5y66p6kwyi

Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation

Yan Chen, Fei Xie, Jin Yang
2008 Proceedings of the 45th annual conference on Design automation - DAC '08  
We optimize both model refinement and spec refinement supported by AutoGSTE: a counterexample-guided refinement loop for GSTE.  ...  In this paper, we present a suite of optimizations targeting automatic abstraction refinement for Generalized Symbolic Trajectory Evaluation (GSTE).  ...  We plot the time and memory usage data for model refinement with and without the precise-nodes-withlifespans optimization in Figure 11 .  ... 
doi:10.1145/1391469.1391508 dblp:conf/dac/ChenXY08 fatcat:x7d3d4exjzahdaio7ydn2t5qfi

Data cache energy minimizations through programmable tag size matching to the applications

Peter Petrov, Alex Orailoglu
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
We target in this work particularly the data cache tag operations and show how an exceedingly small number of tag bits, ifany, are needed to compute the misshit behavior for the vast majority of loagstore  ...  The energy needed to perform the tag reads and comparisons can be thus dramatically reduced.  ...  In [3] a technique for speculation control and pipeline gating has been presented for energy reduction in speculative processors.  ... 
doi:10.1145/500001.500028 fatcat:vb55ut64zzfyvlj6fjkn2h5rza

Data cache energy minimizations through programmable tag size matching to the applications

Peter Petrov, Alex Orailoglu
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
We target in this work particularly the data cache tag operations and show how an exceedingly small number of tag bits, ifany, are needed to compute the misshit behavior for the vast majority of loagstore  ...  The energy needed to perform the tag reads and comparisons can be thus dramatically reduced.  ...  In [3] a technique for speculation control and pipeline gating has been presented for energy reduction in speculative processors.  ... 
doi:10.1145/500024.500028 fatcat:5vsydfowzzejtpkit7m3tny6e4

Speculative Staging for Interpreter Optimization [article]

Stefan Brunthaler
2013 arXiv   pre-print
The key idea is to combine speculative staging of optimized interpreter instructions with a novel technique of incrementally and iteratively concerting them at run-time.  ...  Our technique unites high performance with the simplicity and portability of interpreters---we report that our optimization makes the CPython interpreter up to more than four times faster, where our interpreter  ...  In 1984, Deutsch and Schiffman [16] report that there exists a "dynamic locality of type usage," which enables speculative optimization of code for any arbitrary but fixed and observed type τ .  ... 
arXiv:1310.2300v1 fatcat:opwefwae4zdfhit73ierqczvxe
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