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Residue-to-Binary Converter for the New Moduli Set {� � � � − �, � � , � � � � + �}

H. Siewobr, K. A. Gbolagade
2014 IOSR Journal of VLSI and Signal processing  
Experiments were performed on our converter and the state of the art using Xilinx ISE 14.3 software to target a Spartan 3 FPGA board.  ...  In this paper, we propose the new moduli set { − , , + } with an efficient reverse converter.  ...  INTRODUCTION Arithmetic computations based on Residue Number System (RNS) has found wide spread usage in Digital Signal Processing (DSP) applications such as filtering, computation of the discrete Fourier  ... 
doi:10.9790/4200-04114449 fatcat:dbw32bjpavh4hoisrfxhukdfoa

Mixed-precision weights network for field-programmable gate array

Ninnart Fuengfusin, Hakaru Tamukoh, Chi-Hua Chen
2021 PLoS ONE  
We systematized the accuracy sparsity bit score, which is a linear combination of accuracy, sparsity, and number of bits.  ...  From the software aspect, we evaluated the MPWN on the Fashion-MNIST and CIFAR10 datasets.  ...  Therefore, we implemented MPWN in a field-programmable gate array (FPGA). One advantage of an FPGA over the conventional software language is it enables bitwise manipulation.  ... 
doi:10.1371/journal.pone.0251329 pmid:33970965 pmcid:PMC8109814 fatcat:v5svfwclxjhaxf5bkrfdrwaiqu

Implementation of various data encryption methods for medical information transmission

S Neelima, R Brinda
2018 International Journal of Engineering & Technology  
On the other hand decryption is the reverse process of encryption with help of same key used at encryption or with the help of some other key.  ...  Encryption is the process of converting the data from readable format into unreadable format with help of any mathematical expression or sometimes with the help of key.  ...  The Montgomery Multiplication based on Residue Number Systems with RSA signature in parallel architecture was implemented in FPGA [Mathieu Ciet].  ... 
doi:10.14419/ijet.v7i2.31.13446 fatcat:aiielsjyafhhdadku3nnu7yqfy

Sign Detection and Number Comparison on RNS 3-Moduli Sets $$\{2^n-1, 2^{n+x}, 2^n+1\}$$ { 2 n - 1 , 2 n + x , 2 n + 1 }

Leonel Sousa, Paulo Martins
2016 Circuits, systems, and signal processing  
In this paper, a new method is proposed for sign identification and number comparison based on an optimized version of the mixed radix conversion for the augmented 3-moduli sets {2 n + 1, 2 n − 1, 2 n+  ...  However, while addition, subtraction and multiplication are operations easily and directly performed in parallel on the residues, other arithmetic operations are difficult to implement in RNS, such as  ...  The RNS reverse conversion is a more complex operation that requires not only to apply modular arithmetic but also to combine residues from the different channels.  ... 
doi:10.1007/s00034-016-0354-z fatcat:v3efcs2qqnbmhjfrsbjl4ehtci

Improving Calculation Accuracy of Digital Filters Based on Finite Field Algebra

Kaplun, Aryashev, Veligosha, Doynikova, Lyakhov, Butusov
2019 Applied Sciences  
The possibilities and benefits of optimization of the computational channel structure for digital filter functioning based on the codes of finite field algebra are shown.  ...  The applications of digital filters based on finite field algebra codes require their conjugation with positional computing structures.  ...  To get the modulo residue the arithmetic operations with the number bits are conducted. The type and the number of arithmetic operations depend on the conversion method.  ... 
doi:10.3390/app10010045 fatcat:56lkgb4kdrbp7pb6nh3pdld3vy

$2^n$ RNS Scalers for Extended 4-Moduli Sets

Leonel Sousa
2015 IEEE transactions on computers  
Scaling is a key important arithmetic operation and is difficult to perform in Residue Number Systems (RNS).  ...  Index Terms-Residue number system, scaling, Chinese remainder theorem, VLSI architecture, ASIC, FPGA. ! 0018-9340 (c)  ...  This work was supported by national funds through Fundação para a Ciência e a Tecnologia (FCT) with reference UID/CEC/50021/2013, and project EXPL/EEI-ELC/1572/2013.  ... 
doi:10.1109/tc.2015.2401026 fatcat:4fmxjk3rtnazjn334msaao2ca4

Efficient hardware prototype of ECDSA modules for blockchain applications

Devika K N, Ramesh Bhakthavatchalu
2021 TELKOMNIKA (Telecommunication Computing Electronics and Control)  
Despite ECDSA architecture being computationally expensive, the usage of a dedicated standalone circuit enables speedy execution of arithmetic operations.  ...  This paper concentrates on the hardware implementation of efficient and reconfigurable elliptic curve digital signature algorithm (ECDSA) that is suitable for verifying transactions in Blockchain related  ...  Adoption of efficient algorithms such as Montgomery, residue number system (RNS) or interleaved modular multiplication can improve the latency and speed of computational process [28] - [34] .  ... 
doi:10.12928/telkomnika.v19i5.19416 fatcat:dq2gw5pbcvcojgiqhrcjgnijlu

Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic

Alan Daly, William Marnane
2002 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02  
This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on FPGA (Field Programmable Gate Array).  ...  Speed and area comparisons are performed on the optimised designs.  ...  an integer to it's M -residue as follows: MonPro (A, r 2 , M ) = Ar 2 r −1 mod M = Ar mod M = A So to convert a number, A, to it's M -residue, A, it is necessary to compute MonPro (A, r 2 , M ).  ... 
doi:10.1145/503053.503055 fatcat:v463j5r37je4pkbaefetlxjcli

Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic

Alan Daly, William Marnane
2002 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02  
This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on FPGA (Field Programmable Gate Array).  ...  Speed and area comparisons are performed on the optimised designs.  ...  an integer to it's M -residue as follows: MonPro (A, r 2 , M ) = Ar 2 r −1 mod M = Ar mod M = A So to convert a number, A, to it's M -residue, A, it is necessary to compute MonPro (A, r 2 , M ).  ... 
doi:10.1145/503048.503055 dblp:conf/fpga/DalyM02 fatcat:r647r4flabdvdebbszen55flae

CIDPro: Custom Instructions for Dynamic Program Diversification [article]

Thinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew-Kei Lam, and Nandeesha Veeranna
2018 arXiv   pre-print
CIDPro has been implemented on the Zynq7000 XC7Z020 FPGA device to study the performance overhead and security tradeoffs.  ...  on each execution instance.  ...  The hardware resource utilization is reported in terms of the number of slices and DSP blocks for FPGA implementation on the Zynq7000 FPGA device.  ... 
arXiv:1809.01221v1 fatcat:ou3yp4pnonho3crfukhpzzrcd4

Time Efficient Dual-Field Unit for Cryptography-Related Processing [chapter]

Alessandro Cilardo, Nicola Mazzocca
2010 IFIP Advances in Information and Communication Technology  
Computational demanding public key cryptographic algorithms, such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve (EC) cryptosystems, are critically dependent on modular multiplication for their performance  ...  Furthermore, it relies on a modified Booth recoding scheme for the multiplicand and a radix-4 scheme for the modulus, enabling reduced time delays even for moderately large operand widths.  ...  An interesting property enabled by Montgomery multiplication is the possibility to work on N -residues of numbers, defined as A = A·R mod N .  ... 
doi:10.1007/978-3-642-12267-5_11 fatcat:47kgsgd2ina5tbfoowq474lw6m

Final Statements [chapter]

2009 FPGA-Based Implementation of Signal Processing Systems  
The authors would like to thank Richard Walke and John Gray for motivating a lot of the work at Queen's University Belfast on FPGA.  ...  A number of other people have also acted to contribute in many other ways to either provide technical input or support. These  ...  However, with FPGA platforms, the choice of arithmetic can have a much wider impact on the performance cost right through the design process; though to be fair, architectural decisions made by FPGA vendors  ... 
doi:10.1002/9780470713785.ch14 fatcat:b5uyg6k2qbhnncscazm2ickxki

An Experimental Study of Building Blocks of Lattice-Based NIST Post-Quantum Cryptographic Algorithms

Malik Imran, Zain Ul Abideen, Samuel Pagliarini
2020 Electronics  
interesting insights about the relative importance of each building block for the overall cryptosystem, which can be used for guiding ASIC designers when selecting an algorithm or when deciding where to focus optimization  ...  Similar to FPGA-based implementations, RTL is generated through HLS by the authors of [23, 24] where they also evaluate different design characteristics.  ...  One approach to perform reduction is to perform bitwise XOR operation over first m bits of s with cyclic shifts to left on the remaining n bits of s and repeated until all n bits of s are processed.  ... 
doi:10.3390/electronics9111953 fatcat:vhy3rkjlq5cqvodm74jvtnaawq

Hardware architectures for public key cryptography

Lejla Batina, Sıddıka Berna Örs, Bart Preneel, Joos Vandewalle
2003 Integration  
RSA and Elliptic Curve Cryptography (ECC), both based on modular arithmetic. We first discuss the mathematical background and the algorithms to implement these cryptosystems.  ...  The operations used for RSA and ECC are derived from number theory and create the next level. Beyond the level of number theory we run into levels that deal with implementation issues.  ...  The arithmetic processor includes the subsystems such as: The arithmetic processor is implemented on FPGA based using Xilinx XC4020XL.  ... 
doi:10.1016/s0167-9260(02)00053-6 fatcat:u5pkdeitprh77hcaaui66nzv24

An Instruction Set Extension to Support Software-Based Masking

Si Gao, Johann Großschädl, Ben Marshall, Dan Page, Thinh Pham, Francesco Regazzoni
2021 Transactions on Cryptographic Hardware and Embedded Systems  
Focusing on software, however, the use of masking can present various challenges: specifically, it often 1) requires significant effort to translate any theoretical security properties into practice, and  ...  arithmetic shares, and finally converting the arithmetic shares of the sum back to Boolean shares.  ...  When a block cipher involves both Boolean and arithmetic operations, it is necessary to convert the masks from one form to the other to obtain the correct ciphertext (or plaintext).  ... 
doi:10.46586/tches.v2021.i4.283-325 fatcat:phlwy2wppng23lhvgpgep4uixa
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