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Dynamic global buffer planning optimization based on detail block locating and congestion analysis

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, C. K. Cheng, Jun Gu
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Since there is more freedom for floorplan optimization, the floorplanning algorithm integrated with buffer planning can result in better performance and chip area.  ...  The buffer insertion will affect the possible routes as well the congestion of the packing. The congestion estimation in this paper takes the buffer insertion into account.  ...  Based on this floorplan, we assign target delays to the two-pin nets as follows: for each net, we first compute its best delay by optimal buffer insertion Topt, and assign its target delay as 1.1Topt.  ... 
doi:10.1145/775832.776036 dblp:conf/dac/MaHDCCCG03 fatcat:if43j64y3ferfm2tbedx2xuiuq

Dynamic global buffer planning optimization based on detail block locating and congestion analysis

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, C. K. Cheng, Jun Gu
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Since there is more freedom for floorplan optimization, the floorplanning algorithm integrated with buffer planning can result in better performance and chip area.  ...  The buffer insertion will affect the possible routes as well the congestion of the packing. The congestion estimation in this paper takes the buffer insertion into account.  ...  Based on this floorplan, we assign target delays to the two-pin nets as follows: for each net, we first compute its best delay by optimal buffer insertion Topt, and assign its target delay as 1.1Topt.  ... 
doi:10.1145/776033.776036 fatcat:orfvw7qt2fhy5hjjdeqfmd73bq

Routability driven floorplanner with buffer block planning

Chiu Wing Sham, Evangeline F. Y. Young
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
In the congestion optimization phase, a floorplan will be evaluated by its area, wirelength, congestion, and routability.  ...  Our method is based on a simulated annealing approach that is divided into two phases: the area optimization and congestion optimization phases.  ...  The algorithm is shown as In our design, the simulated annealing process is divided into two phases. They are the area optimization phase and the congestion optimization phase.  ... 
doi:10.1145/505388.505402 dblp:conf/ispd/ShamY02 fatcat:jeka2s5dnfecbj2zjfslfcybem

Routability driven floorplanner with buffer block planning

Chiu Wing Sham, Evangeline F. Y. Young
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
In the congestion optimization phase, a floorplan will be evaluated by its area, wirelength, congestion, and routability.  ...  Our method is based on a simulated annealing approach that is divided into two phases: the area optimization and congestion optimization phases.  ...  The algorithm is shown as In our design, the simulated annealing process is divided into two phases. They are the area optimization phase and the congestion optimization phase.  ... 
doi:10.1145/505401.505402 fatcat:tje7mmqz4vhuratg4bjile57bm

Routability-driven floorplanner with buffer block planning

Chiu-Wing Sham, E.F.Y. Young
2003 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In the congestion optimization phase, a floorplan will be evaluated by its area, wirelength, congestion, and routability.  ...  Our method is based on a simulated annealing approach that is divided into two phases: the area optimization and congestion optimization phases.  ...  The algorithm is shown as In our design, the simulated annealing process is divided into two phases. They are the area optimization phase and the congestion optimization phase.  ... 
doi:10.1109/tcad.2003.809649 fatcat:bgqlkykd2ffnvkgdsqwcg43pjy

Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs

Byung-Gyu Ahn, Jae-Hwan Kim, Wenrui Li, Jong-Wha Chong
2011 JSTS Journal of Semiconductor Technology and Science  
In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage.  ...  Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost.  ...  After the virtual pin assignment, virtual routing is constructed based on the Minimum Steiner Tree. In 3D ICs, the length of TSVs is insignificant comparing with the length of signal nets.  ... 
doi:10.5573/jsts.2011.11.4.344 fatcat:pfxc6skbijchhim4sh2io6r5oy

Fast buffer planning and congestion optimization in interconnect-driven floorplanning

Keith W. C. Wong, Evangeline F. Y. Young
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
Under this buffer insertion constraint, our floorplanner will estimate congestion by computing the best possible buffer locations for each net and perform probabilistic analysis based on the solution.  ...  Nets are topologically grouped to consider bus-based routing and to facilitate the estimation process.  ...  In the global router, multi-pin nets are decomposed into two-pin nets based on the MST method and the two-pin nets are routed one after another by dynamic programming.  ... 
doi:10.1145/1119772.1119854 dblp:conf/aspdac/WongY03 fatcat:z5jw2fxlfjexbaepaacvhj2zpy

Multicommodity Flow Algorithms for Buffered Global Routing [article]

Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky
2005 arXiv   pre-print
, as well as layer and pin assignment.  ...  In this paper we describe a new algorithm for buffered global routing according to a prescribed buffer site map.  ...  The authors wish to thank Charles Alpert, Jason Cong, and Jiang Hu for kindly providing us with the testcases used in [9] and [4] .  ... 
arXiv:cs/0508045v1 fatcat:7nxeyp6sxbfqflrunbztfnctuq

Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign

Ren-Jie Lee, Hung-Ming Chen
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Index Terms-Package-board codesign, pin-block floorplanning, pin-out designation.  ...  The proposed approach can not only automate the assignment of more than 200 input/output (I/O) pins on package, but also precisely evaluate package size which accommodates all pins with almost no void  ...  ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for providing precious comments that greatly improved this paper.  ... 
doi:10.1109/tvlsi.2009.2017795 fatcat:huasjzj6evhutkkhqha6q5qdku

Device-level early floorplanning algorithms for RF circuits

Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley
1998 Proceedings of the 1998 international symposium on Physical design - ISPD '98  
Experimental results demonstrate the ability of this approach to successfully optimize for wire planarity, realize multiple constraints on net lengths or phases, and achieve reasonable area in modest CPU  ...  Each floorplan candidate is fully routed with a gridless, detailed maze-router which can dynamically resize the floorplan as necessary.  ...  Mlinar of HP-EEsof for several insightful discussions of the potential role of genetic optimization in device-level RF layout.  ... 
doi:10.1145/274535.274543 dblp:conf/ispd/AktunaRC98 fatcat:ua6bxiz2gzayhf6hfipat6pwqy

Device-level early floorplanning algorithms for RF circuits

M. Aktuna, R.A. Rutenbar, L.R. carley
1999 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Experimental results demonstrate the ability of this approach to successfully optimize for wire planarity, realize multiple constraints on net lengths or phases, and achieve reasonable area in modest CPU  ...  Each floorplan candidate is fully routed with a gridless, detailed maze-router which can dynamically resize the floorplan as necessary.  ...  Mlinar of HP-EEsof for several insightful discussions of the potential role of genetic optimization in device-level RF layout.  ... 
doi:10.1109/43.752922 fatcat:ujzxgtemknakhp5cga4dgymsji

A pseudo-hierarchical methodology for high performance microprocessor design

A. Bertolet, G. Rodgers, D. Willmott, T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. A. Scott, R. Weiss, K. Carpenter, K. Carrig (+6 others)
1997 Proceedings of the 1997 international symposium on Physical design - ISPD '97  
Critical aspects of the methodology include an integrated database for design control, algorithmic power grid generation, fully customized clock network insertion, timing driven placement and routing,  ...  Because five levels of metal were available for routing, congestion was not a major concern for this design.  ...  This enabled floorplanning, placement, and routing to continue, despite errors, throughout the earlier phases of the integration process to provide valuable timing feedback with routing parasitics.  ... 
doi:10.1145/267665.267702 dblp:conf/ispd/BertoletCCCDFKPPRWBDGLMSW97 fatcat:tyvdnud24fbxvohuufqn2o5tgm

BEAR-FP: A ROBUST FRAMEWORK FOR FLOORPLANNING

MASSOUD PEDRAM, ERNEST S. KUH
1992 International Journal of High Speed Electronics and Systems  
routing and pin assignment.  ...  A systematic and e cient optimization procedure during the selection of suitable oorplan patterns that integrates oorplanning, global routing and pin assignment, a new pin assignment technique based on  ...  After initial pin assignment, global routing on the partial oorplan produces the shortest connection paths for all nets. This routing scheme may result in over-congested channels.  ... 
doi:10.1142/s0129156492000060 fatcat:rpjhsqwenbdalonkrmyfgjpujm

Physical synthesis methodology for high performance microprocessors

Yiu-Hing Chan, Prabhakar Kudva, Lisa Lacey, Greg Northrop, Thomas Rosser
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Physical synthesis techniques were aggressively used as part of logic and placement optimizations for performance, power and area.  ...  After routing is completed, RC netlist extraction is done for post PD timing analysis.  ...  POST PHYSICAL SYNTHESIS After the macros have gone through physical synthesis for optimized books placement with late and early mode timing optimization, the macros go through routing.  ... 
doi:10.1145/775832.776009 dblp:conf/dac/ChanKLNR03 fatcat:csietpybabhuvphfsujlslbfgm

Physical synthesis methodology for high performance microprocessors

Yiu-Hing Chan, Prabhakar Kudva, Lisa Lacey, Greg Northrop, Thomas Rosser
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Physical synthesis techniques were aggressively used as part of logic and placement optimizations for performance, power and area.  ...  After routing is completed, RC netlist extraction is done for post PD timing analysis.  ...  POST PHYSICAL SYNTHESIS After the macros have gone through physical synthesis for optimized books placement with late and early mode timing optimization, the macros go through routing.  ... 
doi:10.1145/776008.776009 fatcat:evw6u26djvdt7d5tp6xxjhsi7a
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