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Reconfigurable Morphological Image Processing Accelerator for Video Object Segmentation

Shao-Yi Chien, Liang-Gee Chen
2008 Journal of Signal Processing Systems  
Therefore, with the concepts of morphological image processing element array and stream processing, a reconfigurable morphological image processing accelerator is proposed, where by the proposed instruction  ...  Furthermore, with the proposed tiling and pipelined-parallel techniques, a realtime watershed transform can be achieved using 32 macro processing elements.  ...  Acknowledgements The authors would like to thank chip implementation center (CIC) for EDA tool and design flow support.  ... 
doi:10.1007/s11265-008-0311-6 fatcat:xvcwwp3ojfcrpervsqfo2blnre

Realizing reconfigurable mesh algorithms on softcore arrays

Heiner Giefers, Marco Platzner
2008 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation  
The reconfigurable mesh is a very popular model for massively parallel computation for which a large body of algorithms with exceptionally low runtime complexities exists.  ...  In this paper, we present the mapping of reconfigurable mesh algorithms to softcore arrays.  ...  Other researchers deal with optical models, e.g., the Linear Array with Reconfigurable Pipelined Bus System (LARPS) [10] .  ... 
doi:10.1109/icsamos.2008.4664845 dblp:conf/samos/GiefersP08 fatcat:353d4qdnxjgafpgkes6vymuzpm

Reconfigurable Architectures [chapter]

Mansureh Shahraki Moghaddam, Jae-Min Cho, Kiyoung Choi
2017 Handbook of Hardware/Software Codesign  
Reconfigurable architecture is a computer architecture combining some of the flexibility of software with the high performance of hardware.  ...  This chapter discusses two major streams of reconfigurable architecture: Field-Programmable Gate Array (FPGA) and Coarse Grained Reconfigurable Architecture (CGRA).  ...  are connected with a shared bus.  ... 
doi:10.1007/978-94-017-7267-9_12 fatcat:bkvbwe3frjhclfdidzburz36ju

Ant Colony Optimal Algorithm: Fast Ants on the Optical Pipelined R-Mesh

Ken D. Nguyen, Anu G. Bourgeois
2006 2006 International Conference on Parallel Processing (ICPP'06)  
In this paper, we demonstrate how to implement and improve two Ant Colony Optimization (ACO) algorithms on the Optical Pipelined Reconfigurable Mesh (PR-Mesh): the generic ACO and the Fast Ant Colony Optimization  ...  Our FACO algorithm on PR-Mesh yields O((( z n·log 2 n )+ n logn ) · loglogn) run-time complexity for n 2 jobs while the existing FACO algorithm on the electrical model yields a run-time complexity of O  ...  The local fusing configures a linear bus connecting neighboring processors. Each such linear bus exactly resembles a Linear Array with a Reconfigurable Bus Systems (LARPBS) [14] .  ... 
doi:10.1109/icpp.2006.24 dblp:conf/icpp/NguyenB06 fatcat:25hepbjxlva5dakwljy2nj4ubu

NeuFlow: A runtime reconfigurable dataflow processor for vision

Clement Farabet, Berin Martini, Benoit Corda, Polina Akselrod, Eugenio Culurciello, Yann LeCun
2011 CVPR 2011 WORKSHOPS  
In this paper we present a scalable dataflow hardware architecture optimized for the computation of generalpurpose vision algorithms-neuFlow-and a dataflow compiler-luaFlow-that transforms high-level flow-graph  ...  representations of these algorithms into machine code for neuFlow.  ...  Many systems have been proposed which are based on two-dimensional arrays of processing elements interconnected by a routing fabric that is reconfigurable.  ... 
doi:10.1109/cvprw.2011.5981829 dblp:conf/cvpr/FarabetMCACL11 fatcat:ytoyo66yjjc3lcrj2oem7s7i4a

Reconfigurable Computing: Viable Applications and Trends [chapter]

Alexandro M. S. Adário, Sergio Bampi
2000 IFIP Advances in Information and Communication Technology  
of a software framework for supporting the reconfiguration paradigm over a wider range of algorithms and applications.  ...  As a radically new architecture approach, reconfiguration has been hindered by a lack of a common development framework and even an unified taxonomy to define the dynamics of the reconfiguration of the  ...  in a pipeline organization with a simplified control.  ... 
doi:10.1007/978-0-387-35498-9_51 fatcat:oqvt7hl3cncanfdztfsv7islhq

Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor

K.s. Tham, D.L. Maskell
2006 2006 International Conference on Field Programmable Logic and Applications  
for reconfigurable systems.  ...  Such reconfigurable systems present a difficult problem for current modeling platforms as a tightly-coupled co-design/simulation effort for both hardware and software must be integrated in the framework  ...  LIST OF FIGURES 2-1 A Run-time System Overview. 6 2-2 Resource models; (a) 2D model (b) 2D fixed block partition 14 I ID variable block partition (d) ID fixed block partition 3-1 FPGA-based architectural  ... 
doi:10.1109/fpl.2006.311230 dblp:conf/fpl/ThamM06 fatcat:jyvrwl33uzcytolxwgywctvmwm

Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

Jean Shilpa V, P.K. Jawahar
2021 International Journal of Systems Control and Communications  
The evaluation for all the algorithm were carried out in zybo board belonging to zynq 7010 family of all programmable system on chip FPGA board, with Xilinx vivado 2014.4 as the development software.  ...  Algorithms have been proposed for efficient utilisation of the proposed hybrid processor to work as a platform of work for the software demanding high speed and performance metrics.  ...  Abdur Rahman Crescent Institute of science and technology for giving an opportunity to evaluate the system using Xilinx Vivado simulator and Zedboard.  ... 
doi:10.1504/ijscc.2021.10035685 fatcat:w3eovue6lndqhnrxman4o7az3q

High Performance Reconfigurable Computing Systems [article]

Issam Damaj
2019 arXiv   pre-print
Many other implementation options present, for instance, a system with a RISC processor and a DSP core. Other options include graphics processors and microcontrollers.  ...  Furthermore, a technical survey of various RC-systems is included laying common grounds for comparisons.  ...  Najjar et al in [67] presented a high-level, algorithmic language and optimizing compiler for the development of image processing applications on RC-systems.  ... 
arXiv:1904.04953v1 fatcat:k5y4cpudi5e6dfqtpizj3z45te

Optically interconnected parallel computing systems

M. Ishikawa, N. McArdle
1998 Computer  
Researchers have developed an architecture for high-speed computation, image processing, and robotic vision systems that uses both the programmability of mature electronic technology and the density and  ...  Board-level connections among multichip modules (MCMs) on boards. • Chip-to-chip connections on a board or MCM. • Gate-to-gate connections within a chip.  ...  of Hamamatsu Photonics for supplying the PAL-SLM and the custom optomechanical system.  ... 
doi:10.1109/2.652923 fatcat:znpbkwoytbeupcvuvnvbxoyvr4

Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems [chapter]

Katherine Compton, Akshay Sharma, Shawn Phillips, Scott Hauck
2002 Lecture Notes in Computer Science  
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides hardware speeds as well as the benefits of post-fabrication modification.  ...  We show that these algorithms provide results with a low area overhead compared to the custom-designed RaPiD routing architecture, as well as the flexibility needed to handle some application modifications  ...  Katherine Compton is supported by a UPR grant from Motorola, Inc. Scott Hauck is supported in part by an NSF CAREER Award and a Sloan Research Fellowship.  ... 
doi:10.1007/3-540-46117-5_8 fatcat:tmtao6jrhjecfc2qqwwmpwm7ea

Configuration relocation and defragmentation for run-time reconfigurable computing

K. Compton, Zhiyuan Li, J. Cooley, S. Knol, S. Hauck
2002 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We therefore present hardware solutions to provide relocation and defragmentation support with a negligible area increase over a generic partially reconfigurable FPGA, as well as software algorithms for  ...  Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research.  ...  For hardware designed specifically with one-dimensionality in mind, the virtualized I/O is also simplified.  ... 
doi:10.1109/tvlsi.2002.1043324 fatcat:sa4tppuug5c6vbr5pzm5v2e2fi

Impact of Reconfigurable Function on Meshes with Row/Column Buses

Susumu Matsumae
2011 International Journal of Networking and Computing  
This paper studies the difference in computational power between the mesh-connected parallel computers equipped with dynamically reconfigurable bus systems and those with static ones.  ...  The mesh with separable buses (MSB) is the mesh-connected computer with dynamically reconfigurable row/column buses.  ...  Acknowledgements This work was partly supported by the MEXT Grant-in-Aid for Young Scientists (B) (20700014).  ... 
doi:10.15803/ijnc.1.1_36 fatcat:i6hmhfkqpfhh5gjdtmccpon3mm

Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing

Zain-ul-Abdin, Bertil Svensson
2009 Microprocessors and microsystems  
., multimedia applications, such as video processing in HDTV, and communication applications, such as baseband processing in telecommunication systems, the architectures of reconfigurable devices have  ...  evolved to coarse-grained compositions of functional units or program controlled processors, which are operated in a coordinated manner to improve performance and energy efficiency.  ...  Dan Hammerstrom) for their valuable feedback during the internal review of the paper.  ... 
doi:10.1016/j.micpro.2008.10.003 fatcat:k4c63f4k2zbc5a4mfr3vfwqkfe

A New FPGA/DSP-Based Parallel Architecture for Real-Time Image Processing

J Batlle
2002 Real-time imaging  
This architecture is structured with a two-dimensional (2D) array of FPGA/DSP-based reprogrammable processors P ij .  ...  in classic crossbar systems such as those which occur with butterfly connections.  ...  This is also a parallel computer based on an SIMD reduced-size array processor with a novel organization of the memory sub-system.  ... 
doi:10.1006/rtim.2001.0273 fatcat:gzpo6lpaongtfiuxd7ph5fvziy
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