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Optimal Live Range Merge for Address Register Allocation in Embedded Programs [chapter]

Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik
2001 Lecture Notes in Computer Science  
It leverages on previous work, which is based on a heuristic that merges address register live ranges.  ...  We prove, for the first time, that the merge operation is NP-hard in general, and show the existence of an optimal linear-time algorithm, based on dynamic programming, for a special case of the problem  ...  We also thank the reviewers for their comments.  ... 
doi:10.1007/3-540-45306-7_19 fatcat:dkwu4ulm3jfdhijysbgridwlb4

Address register allocation for arrays in loops of embedded programs

Guilherme Ottoni, Guido Araujo
2003 Microelectronics Journal  
Efficient address register allocation has been shown to be a central problem in code generation for processors with restricted addressing modes.  ...  This paper extends previous work on Global Array Reference Allocation (GARA), the problem of allocating address registers to array references in loops.  ...  We would like to thank Gang-Ryung Uh from Agere Systems Inc. for his support on the DSP16xx processor, and Michael Collison from Mindspeed, Inc. for creating and maintaining the DSP16xx GCC port.  ... 
doi:10.1016/s0026-2692(03)00169-1 fatcat:f232uwx6wbarbdxcbeehfhqhcy

Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms

Jeonghun Cho, Yunheung Paek, David Whalley
2002 Proceedings of the joint conference on Languages, compilers and tools for embedded systems software and compilers for embedded systems - LCTES/SCOPES '02  
Finding an optimal assignment of program variables into registers and memory is prohibitively difficult in code generation for application specific instruction-set processors (ASIPs).  ...  This is mainly because, in order to meet stringent speed and power requirements for embedded applications, ASIPs commonly employ non-orthogonal architectures which are typically characterized by irregular  ...  Not only can the compiler merge nonconflicting live ranges of the same variable, as in the case of the variable a, but it can also merge nonconflicting live ranges of different variables.  ... 
doi:10.1145/513852.513853 fatcat:ehjdpzsvmzc5xktkl3uks7xjfy

Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms

Jeonghun Cho, Yunheung Paek, David Whalley
2002 Proceedings of the joint conference on Languages, compilers and tools for embedded systems software and compilers for embedded systems - LCTES/SCOPES '02  
Finding an optimal assignment of program variables into registers and memory is prohibitively difficult in code generation for application specific instruction-set processors (ASIPs).  ...  This is mainly because, in order to meet stringent speed and power requirements for embedded applications, ASIPs commonly employ non-orthogonal architectures which are typically characterized by irregular  ...  Not only can the compiler merge nonconflicting live ranges of the same variable, as in the case of the variable a, but it can also merge nonconflicting live ranges of different variables.  ... 
doi:10.1145/513829.513853 dblp:conf/lctrts/ChoPW02 fatcat:ylwlivg2yraspdjpquylz7n5ku

Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms

Jeonghun Cho, Yunheung Paek, David Whalley
2002 SIGPLAN notices  
Finding an optimal assignment of program variables into registers and memory is prohibitively difficult in code generation for application specific instruction-set processors (ASIPs).  ...  This is mainly because, in order to meet stringent speed and power requirements for embedded applications, ASIPs commonly employ non-orthogonal architectures which are typically characterized by irregular  ...  Not only can the compiler merge nonconflicting live ranges of the same variable, as in the case of the variable a, but it can also merge nonconflicting live ranges of different variables.  ... 
doi:10.1145/566225.513853 fatcat:otmh5phagfgdniuhix26i3uety

Dynamic overlay of scratchpad memory for energy minimization

Manish Verma, Lars Wehmeyer, Peter Marwedel
2004 Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04  
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems.  ...  Moreover, there exists a large potential for optimizing the energy consumption of the memory subsystem.  ...  In the recent past, approaches for optimal register allocation [1, 8, 11] have been proposed.  ... 
doi:10.1145/1016720.1016748 dblp:conf/codes/VermaWM04 fatcat:jrwyorhpbvawvnp5csuieix3au

Eliminating the call stack to save RAM

Xuejun Yang, Nathan Cooprider, John Regehr
2009 Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems - LCTES '09  
Most programming languages support a call stack in the programming model and also in the runtime system.  ...  optimizations.  ...  Acknowledgments The authors would like to thank Yang Chen, Mary Hall, Matthew Might, Jon Rafkind, and Alastair Reid for their invaluable help and advice.  ... 
doi:10.1145/1542452.1542461 dblp:conf/lctrts/YangCR09 fatcat:7mmafozivvhdln63uivxm7ebom

Eliminating the call stack to save RAM

Xuejun Yang, Nathan Cooprider, John Regehr
2009 SIGPLAN notices  
Most programming languages support a call stack in the programming model and also in the runtime system.  ...  optimizations.  ...  Acknowledgments The authors would like to thank Yang Chen, Mary Hall, Matthew Might, Jon Rafkind, and Alastair Reid for their invaluable help and advice.  ... 
doi:10.1145/1543136.1542461 fatcat:r7lxbsho7rdd7jlgnn3zplmh3m

RL4ReAl: Reinforcement Learning for Register Allocation [article]

S. VenkataKeerthy, Siddharth Jain, Rohit Aggarwal, Albert Cohen, Ramakrishna Upadrasta
2022 arXiv   pre-print
We propose a novel solution for the Register Allocation problem, leveraging multi-agent hierarchical Reinforcement Learning.  ...  Experimental results match or outperform the LLVM register allocators, targeting Intel x86 and ARM AArch64.  ...  We plan to address other sub-tasks of register allocation: coalescing, multi-allocation and register packing. We will open-source the framework in the near future.  ... 
arXiv:2204.02013v1 fatcat:js7g5rx5czeybnyumfqtw36kli

Sifting out the mud

Bjorn De Sutter, Bruno De Bus, Koen De Bosschere
2002 Proceedings of the 17th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications - OOPSLA '02  
We have incorporated these techniques in Squeeze++, a prototype link-time binary rewriter for the Alpha architecture, and extensively evaluate them on a suite of 8 real-life C++ applications.  ...  This contrasts with the increasing need for additional functionality and the need for rapid application development.  ...  De Bus is supported by a grant from the 'Flemisch Institute for the Promotion of the Scientific Technological Research in the Industry' (IWT).  ... 
doi:10.1145/582442.582445 fatcat:gtehre5kibbd3bdqr3dqgumwue

Sifting out the mud

Bjorn De Sutter, Bruno De Bus, Koen De Bosschere
2002 SIGPLAN notices  
We have incorporated these techniques in Squeeze++, a prototype link-time binary rewriter for the Alpha architecture, and extensively evaluate them on a suite of 8 real-life C++ applications.  ...  This contrasts with the increasing need for additional functionality and the need for rapid application development.  ...  De Bus is supported by a grant from the 'Flemisch Institute for the Promotion of the Scientific Technological Research in the Industry' (IWT).  ... 
doi:10.1145/583854.582445 fatcat:vufwprbeq5hixd7lmta4obomlu

Sifting out the mud

Bjorn De Sutter, Bruno De Bus, Koen De Bosschere
2002 Proceedings of the 17th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications - OOPSLA '02  
We have incorporated these techniques in Squeeze++, a prototype link-time binary rewriter for the Alpha architecture, and extensively evaluate them on a suite of 8 real-life C++ applications.  ...  This contrasts with the increasing need for additional functionality and the need for rapid application development.  ...  De Bus is supported by a grant from the 'Flemisch Institute for the Promotion of the Scientific Technological Research in the Industry' (IWT).  ... 
doi:10.1145/582419.582445 dblp:conf/oopsla/SutterBB02 fatcat:266odid53zhbhauxf2xbyvjg5u

A fast, memory-efficient register allocation framework for embedded systems

Sathyanarayanan Thammanur, Santosh Pande
2004 ACM Transactions on Programming Languages and Systems  
These attributes make the allocator an attractive candidate for performing a fast, memory-efficient register allocation for embedded devices with a small number of registers.  ...  The main attraction of the allocator is that it does not make use of the traditional live range and interval analysis nor does it perform advanced optimizations based on range splitting but results in  ...  Live Range Splitting In this section, we informally show that our algorithm is able to achieve the property of live range splitting which is essential for good register allocation.  ... 
doi:10.1145/1034774.1034776 fatcat:b5knvmllrfdirlvgl3pwft7mdi

Code optimization techniques for embedded DSP microprocessors

Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
We address the problem of code optimization for embedded DSP microprocessors.  ...  In addition to instruction scheduling and register allocation, we also formulate the accumulator spilling and mode selection problems that arise in DSP microprocessors.  ...  ACKNOWLEDGEMENTS This research was supported in part by the Advanced Research Projects Agency under contract DABT63-94-C-0053, and in part by a NSF Young Investigator Award with matching funds from Mitsubishi  ... 
doi:10.1145/217474.217596 dblp:conf/dac/LiaoDKTW95 fatcat:afom4kbl6zcxznqgo2bpokhdnm

Code Optimization Techniques for Embedded DSP Microprocessors

Stan Liao
1995 Proceedings - Design Automation Conference  
We address the problem of code optimization for embedded DSP microprocessors.  ...  In addition to instruction scheduling and register allocation, we also formulate the accumulator spilling and mode selection problems that arise in DSP microprocessors.  ...  ACKNOWLEDGEMENTS This research was supported in part by the Advanced Research Projects Agency under contract DABT63-94-C-0053, and in part by a NSF Young Investigator Award with matching funds from Mitsubishi  ... 
doi:10.1109/dac.1995.250017 fatcat:dfrq3kjjbndsvjk4pbir7gphwa
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