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One Byte per Clock: A Novel RC4 Hardware [chapter]

Sourav Sen Gupta, Koushik Sinha, Subhamoy Maitra, Bhabani P. Sinha
2010 Lecture Notes in Computer Science  
In this paper, we take a fresh look at the hardware implementation of RC4 and propose a novel architecture which generates 1 keystream byte per clock cycle.  ...  In case of a special purpose hardware designed for RC4, the best known implementation till date is 1 byte per 3 clock cycles.  ...  Our architecture performs the KSA stage of RC4 at a rate of "one round per clock" and produces "one byte per clock" in case of the PRGA routine.  ... 
doi:10.1007/978-3-642-17401-8_24 fatcat:kkajuyhif5f2zkxqg36ej2jdne

Novel Hardware Implementation of Modified RC4 Stream Cipher for Wireless Network Security

N. B.Hulle, R. D. Kharadkar, A. Y. Deshmukh
2012 International Journal of Computer Applications  
This paper presents novel hardware implementation of modified RC4 stream cipher for wireless network security.  ...  This architecture achieved throughput of 63.449 Mbps at a clock frequency of 190.349 MHz independent of key length.  ...  CONCLUSION A novel hardware implementation of the modified RC4 stream cipher algorithm for wireless network security is presented in this paper.  ... 
doi:10.5120/7197-9973 fatcat:r67rjnuvbnhgleevb5c6a4fin4

Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock [article]

Rourab Paul, Hemanta Dey, Amlan Chakrabarti, Ranjan Ghosh
2016 arXiv   pre-print
The hardware designs are appropriately upgraded to accelerate RC4 further by processing 2 onsecutive RC4 bytes together and it has been possible to achieve a maximum throughput of 8-bytes per clock in  ...  on accelerating RC4 by processing bytes in byte-by-byte mode achieving throughputs from 1-byte-in-1-clock to 4-bytes-in-1-clock.  ...  Rising edge of φ 3 : j 5 Fig. 18: 2 2 RC4 co-processor with main processor CKP and 1 S-Box, (D3) 2-bytes per clock with CKP and 1 S-Box, (D4) 2-bytes per clock with CKP and 2 S-Boxes, (D5) 4-bytes per  ... 
arXiv:1609.01389v2 fatcat:ukelfmwmqbg4fngyvto6752oau


Mohamed Nabil, Alaa Eldin Rohiem
2007 International Conference on Aerospace Sciences and Aviation Technology  
In this work, a proposed hardware implementation of RC4 algorithm on field programmable gate arrays (FPGAs) is introduced.  ...  The implementation of cryptographic algorithms on reconfigurable hardware devices based on Field Programmable Gate Arrays (FPGA) devices is highly attractive.  ...  CONCLUSION This paper presents a hardware implementation for one of the most powerful stream ciphers, that is known as RC4.  ... 
doi:10.21608/asat.2007.24121 fatcat:rqg3cob6ondjlhf75chg4xme2i

RC4-AccSuite: A Hardware Acceleration Suite for RC4-Like Stream Ciphers

Ayesha Khalid, Goutam Paul, Anupam Chattopadhyay
2017 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
novel.  ...  Extending on these lines, throughput was improved to 2 cycles per byte using a tri-ported SRAM [31] .  ... 
doi:10.1109/tvlsi.2016.2606554 fatcat:7srflbyyyrftrfhpkpm5a7mupe

WLAN security processor

N. Smyth, M. McLoone, J.V. McCanny
2006 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
A novel wireless local area network (WLAN) security processor is described in this paper.  ...  Existing solutions to wireless security have been implemented on hardware devices and target specific WLAN protocols whereas the programmable security processor proposed in this paper provides support  ...  This RC4 core comprises a 256-byte dual-port RAM used to store the RC4 state array.  ... 
doi:10.1109/tcsi.2006.877888 fatcat:2gvkvjp4izardgdi46evsadr2e

Designing integrated accelerator for stream ciphers with structural similarities

Sourav Sen Gupta, Anupam Chattopadhyay, Ayesha Khalid
2012 Cryptography and Communications  
We propose HiPAcc-LTE, a high performance integrated design that combines the two ciphers in hardware, based on their structural similarities.  ...  Long term vision of this hardware integration approach for cryptographic primitives is to build a flexible core supporting multiple designs having similar algorithmic structures.  ...  Memory Access: We propose a novel pipeline distribution (as shown in Fig. 16 ) of the data-path and re-use both P and Q memories of HC-128 to obtain 1 byte per 2 cycle throughput.  ... 
doi:10.1007/s12095-012-0074-6 fatcat:vapjaw7vbnbvnc22uideavxrca

Encryption overhead in embedded systems and sensor network nodes

Ramnath Venugopalan, Prasanth Ganesan, Pushkin Peddabachagari, Alexander Dean, Frank Mueller, Mihail Sichitiu
2003 Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03  
RC4 is shown to outperform RC5 for the Atmega platform.  ...  The objective of this work is to cover a wide class of commonly used encryption algorithms and to determine the impact of embedded architectures on their performance.  ...  Hence, narrow bus low-end processors may provide higher throughput per clock cycle at a low clock rate while high-end architectures provide higher throughput per time unit at high clock rates.  ... 
doi:10.1145/951710.951737 dblp:conf/cases/VenugopalanGPDMS03 fatcat:fncmkibsebfbtaa5z36cto7mba

Remotely Keyed Cryptographics Secure Remote Display Access Using (Mostly) Untrusted Hardware [chapter]

Debra L. Cook, Ricardo Baratto, Angelos D. Keromytis
2005 Lecture Notes in Computer Science  
We focus on secure video broadcasts and remote desktop access when using any convenient, and often untrusted, terminal as two example applications.  ...  Specifically, to prevent spyware on untrusted clients from accessing the user's data, we restrict the boundary of trust to the client's GPU by moving image decryption into GPUs.  ...  The operations in RC4 consist entirely of adding two bytes, modulo 256 and swapping two bytes. Thus, the only operation required of RC4 which is lacking in a GPU is modular arithmetic.  ... 
doi:10.1007/11602897_31 fatcat:ky56oqtjbjdebk4pgkdgub7czm

A Deep Learning-Based FPGA Function Block Detection Method with Bitstream to Image Transformation [article]

Minzhen Chen, Peng Liu
2021 arXiv   pre-print
In this paper, we propose a novel deep learning-based FPGA function block detection method with three major steps.  ...  on Xilinx Zynq-7000 SoCs and Zynq UltraScale+ MPSoCs.  ...  Each slice in a one-slice CLB is allocated s=4p×n bytes.  ... 
arXiv:2007.11434v2 fatcat:3fxmmylvdzbhjk4a4vnszaq7cy

Overview of securing multimedia content using efficient encryption methods and modes

K. John Singh, Kunal Gagneja
2017 International Journal of Advanced and Applied Sciences  
In this paper, possibilities of securing multimedia data using various encryption methods and modes are analyzed and compared on the basis of their execution speed, hardware implementation and various  ...  Use of multimedia is increasing because of improvements in hardware, algorithms and networking.  ...  Symmetric key ciphers have higher throughput, which can go up to gigabytes per second in hardware implementations.  ... 
doi:10.21833/ijaas.2017.010.013 fatcat:kiebkobk5remfjnn7uwrw7q3hu

A Study on Current Scenario of Audio Encryption

Rashmi A.Gandhi, Atul M. Gosai
2015 International Journal of Computer Applications  
The algorithm is based on a random permutation. The period of cipher is greater than 10 100 . Eight to sixteen machine operations are required per output byte. It is simple and quite easy to explain.  ...  RC4 RC4 [11] is a stream cipher designed in 1987 by Ron Rivest for RSA Security. It is officially termed as "Rivest Cipher 4". It is a variable key-size stream cipher with byte-oriented operations.  ... 
doi:10.5120/20347-2533 fatcat:yxyh32delzddnkgkgbszuri274

PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC

K. Rahimunnisa, P. Karthigaikumar, N. Christy, S. Kumar, J. Jayakumar
2013 Open Computer Science  
throughput of 59.59 Gbps at a frequency of 450.045 MHz on FPGA Virtex XC6VLX75T which is higher than the throughput yielded in other architectures.  ...  In ASIC 0.13 µm technology, the proposed architecture yielded a throughput of 25.60 Gbps and in 0.18 µm, it yielded a throughput of 20.56 Gbps.  ...  Xinmiao Zhang [20] presents novel high speed architectures for the hardware implementation of the AES algorithm.  ... 
doi:10.2478/s13537-013-0112-2 fatcat:u2gerokosffona5iwjdb3wqq4u

Hardware Framework for the Rabbit Stream Cipher [chapter]

Deian Stefan
2010 Lecture Notes in Computer Science  
On the Xilinx Virtex-5 LXT FPGA, a direct, resource-efficient (568 slices) implementation delivers throughputs of up to 9.16 Gbits/s, a 4-slow interleaved design reaches 25.62 Gbits/s using 1163 slices  ...  Previous software implementations have demonstrated Rabbit's high throughput, however, the performance in hardware has only been estimated.  ...  Rabbit performs very well in software (e.g., 5.1 cycles/byte on a 1.7 GHz Pentium 4 and 3.8 cycles/byte on a 533 MHz PowerPC 440GX [6] ) and detailed cryptanalysis by the designers and recent studies  ... 
doi:10.1007/978-3-642-16342-5_17 fatcat:vm643x2prfc6ncyfy6jfdhgzne

A chaotic encryption scheme for real-time embedded systems: design and implementation

Amit Pande, Joseph Zambreno
2011 Telecommunications Systems  
The proposed cipher gives 16 bits of encrypted data per clock cycle.  ...  The hardware implementation results over Xilinx Virtex-6 FPGA give a synthesis clock frequency of 93 MHz and a throughput of 1.5 Gbps while using 16 hardware multipliers.  ...  Attack has been mounted on RC4, PANAMA, FISH etc (not in real-time) but they use a very large internal state (and thus require large more hardware resources).  ... 
doi:10.1007/s11235-011-9460-1 fatcat:issck3pyd5fjbeum3ggpz6xe64
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