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On-Chip Test Circuit for Measuring Substrate and Line-to-Line Coupling Noise

W. Xu, E.G. Friedman
2006 IEEE Journal of Solid-State Circuits  
An on-chip test circuit has been developed to directly measure substrate and line-to-line coupling noise.  ...  On-chip analog-to-digital conversion and calibration are used to eliminate off-chip noise and to extend the measurement accuracy by removing system noise.  ...  ON-CHIP SUBSTRATE COUPLING NOISE TEST TECHNIQUE A specialized on-chip test circuit has been developed to directly measure substrate coupling noise.  ... 
doi:10.1109/jssc.2005.862349 fatcat:ulxz4ss26zgrpku554ayowg5su

Noise generation and coupling mechanisms in deep-submicron ICs

X. Aragones, J.L. Gonzalez, F. Moll, A. Rubio
2002 IEEE Design & Test of Computers  
On-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity.  ...  Selecting adequate test techniques depends on the circuit, its implementation, and the possible physical failures and parasitic coupling models.  ...  Acknowledgments This work has been partially supported by the Spanish Ministry of Science and Technology, and the Regional European Development Funds (FEDER) from the European Union through project TIC2001  ... 
doi:10.1109/mdt.2002.1033789 fatcat:uisvnvukkbbejdy65sc65g24eq

A method for measuring substrate noise in the UWB frequency band on lightly doped substrates

Ming Shen, Tian Tong, Jan Hvolgaard Mikkelsen, Torben Larsen
2007 Norchip 2007  
In addition, the effects of the distance-based substrate resistance and the capacitive coupling between the substrate and the ground of the measurement setup are evaluated by on-wafer measurement of a  ...  test chip fabricated in a 0.18 µm lightly doped CMOS process.  ...  ACKNOWLEDGMENT The authors would like to thank Daniel Sira for design of the class-E PA, Yonghui Huang for helpful discussion and Peter Boie Jensen for bonding of the chip.  ... 
doi:10.1109/norchp.2007.4481057 fatcat:qv3scahksrfmfgytqm2g7bqbxe

Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's

S. Bronckers, C. Soens, G. van der Plas, G. Vandersteen, Y. Rolain
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
This paper presents a methodology for the analysis and prediction of the impact of wideband substrate noise on a LC-Voltage Controlled Oscillator (LC-VCO) from DC up to Local Frequency (LO).  ...  The impact of substrate noise is modeled a priori in a high-ohmic 0.18µm 1P6M CMOS technology and then verified on silicon on a 900MHz LC-VCO.  ...  Better insight in the coupling mechanisms of substrate noise to the analog/RF circuit will help the designer to take the appropriate measures to make their analog circuit more immune to problems of substrate  ... 
doi:10.1109/date.2007.364516 fatcat:qc5siv2kvbfrtclxx64fcffa74

Design of on-chip sensors to monitor electromagnetic activity in ICs: Towards on-line diagnosis and self-healing

S. Ben Dhia, A. Boyer
2014 2014 15th Latin American Test Workshop - LATW  
This paper presents an on-chip noise sensor dedicated to the study of various aspects of electromagnetic compatibility at circuit level, such as power and signal integrity, substrate coupling, conducted  ...  On-chip characterization of noise becomes necessary for model validation and design optimization to reduce redesign costs and time-to-market for IC manufacturers.  ...  For this purpose, a test chip has been designed core in a 0.25 µm SMARTMOS technology test chip from Freescale. The circuit contains 32 on-chip sensors placed on various lines and digital buses.  ... 
doi:10.1109/latw.2014.6841898 dblp:conf/latw/DhiaB14 fatcat:ckqut3aq3bakbgqkstxz2x2i7q

Monolithic Integration of a Folded Dipole Antenna With a 24-GHz Receiver in SiGe HBT Technology

Erik Ojefors, Ertugrul Sonmez, Sbastien Chartier, Peter Lindberg, Christoph Schick, Anders Rydberg, Hermann Schumacher
2007 IEEE transactions on microwave theory and techniques  
A high-resistivity silicon substrate (1000 cm) is used for the implemented circuit to improve the efficiency of the integrated antenna.  ...  His main fields of research are analog and mixed-signal silicon bipolar MMICs for fiber-optical communication systems. , where he focuses on heterostructure transistors and their circuit applications.  ...  ACKNOWLEDGMENT The authors would like to thank Dr. W. Schwerzel, Atmel GmbH, Heilbronn, Germany, for arranging space on wafer runs.  ... 
doi:10.1109/tmtt.2007.900315 fatcat:wjqgu7mq7fdqlfxw5s7mqzo3lq

A measurement fixture suitable for measuring substrate noise in the UWB frequency band

Ming Shen, Tian Tong, Jan H. Mikkelsen, Torben Larsen
2008 Analog Integrated Circuits and Signal Processing  
Signals coupling through the substrate are usually fairly weak and special precautions are taken to avoid any distortions that may be caused by the test fixture.  ...  This paper presents a measurement fixture suitable for measuring substrate carried noise for lightly doped substrates within the UWB frequency band.  ...  discussion and Peter Boie Jensen for bonding of the chip.  ... 
doi:10.1007/s10470-008-9181-x fatcat:2olstcnkrbfjhmyhtq765xxlku

3 Gb/s AC Coupled Chip-to-Chip Communication Using a Low Swing Pulse Receiver

L. Luo, J.M. Wilson, S.E. Mick, J. Xu, L. Zhang, P.D. Franzon
2006 IEEE Journal of Solid-State Circuits  
For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate.  ...  Using this receiver, 3 Gb/s chip-to-chip communication is demonstrated through a wirebonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines.  ...  Bashirullah for their valuable discussions and measurement help on this work. Also, the authors would like to thank J. Diepenbrock of IBM's Integrated Supply Chain for the use of their test equipment.  ... 
doi:10.1109/jssc.2005.859881 fatcat:sec3rbcujbba7j47lk3fqk3kfe

Effect of Simultaneous Switching Noise on an Analog Filter

Erik Backenius, Mark Vesterbacka, Robert Hagglund
2006 2006 13th IEEE International Conference on Electronics, Circuits and Systems  
The measured noise on the output of the analog filter was reduced by 30% up to 50% when the method was used.  ...  Conventional substrate noise reduction methods are used, e.g., separate power supplies, guard rings, and multiple pins for power supplies.  ...  Test Pattern Input pads on chip generally have a large capacitive coupling to the substrate. Therefore, any transition on a pad is coupled to the substrate.  ... 
doi:10.1109/icecs.2006.379934 dblp:conf/icecsys/BackeniusV06 fatcat:i3ipkavgvrez7a2cd2l7qk33xa

Reduction of Simultaneous Switching Noise in Digital Circuits

E. Backenius, M. Vesterbacka
2006 2006 NORCHIP  
In this paper we present results from measurements on a test chip used to evaluate our method for reduction of substrate noise that originates from the clock in digital circuits.  ...  The measured substrate noise on the test chip was reduced by 20% and up to 54%. With optimized clock buffers this method has a potential of an even larger noise reduction.  ...  Therefore the voltage fluctuations on the on-chip ground will be directly coupled to the substrate.  ... 
doi:10.1109/norchp.2006.329207 fatcat:bxffbakz2bbrfnagruvoe36ksy

Modeling and analysis of multichip module power supply planes

Keunmyung Lee, A. Barber
1995 IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B  
It is compatible with a SPICE based modeling method for the rest of the power supply hierarchy and the devices. A modified SPICE is used to accommodate distributed circuits.  ...  The modeling process is described and examples of thick and thin film power supply planes are presented with comparison to measured results.  ...  Acknowledgment The authors would like to thank Dan Miller of Computer Peripherals Lab, HP Laboratories for the design and fabrication of the thick film test substrate.  ... 
doi:10.1109/96.475268 fatcat:byszx3hnlncw5ovuldv4laml2m

Calibrated Tuner for Chip Characterization Above 18 GHz

Sander Weinreb, Bevan Bates, Ronald Harris
1987 29th ARFTG Conference Digest  
The device integrates a three-stub waveguide tuner, a waveguide-to-microstrip adapter, a DC bias tee, and a removable chip-carrier into one compact unit.  ...  A device which produces a known, mechanically-variable impedance and is useful for noise parameter or power load-pull measurements is described.  ...  One useful test which has not yet been performed is to measure the noise parameters over a range of frequencies and look for a smooth frequency variation.  ... 
doi:10.1109/arftg.1987.323864 fatcat:2k3echhvfzgspphst2b74rorea

Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply

2006 IEICE transactions on electronics  
Our first trial shows that 34% substrate noise reduction is achieved on our test circuit, and the theoretical analysis shows that the optimized canceller design will enhance the substrate noise suppression  ...  on the ground line impedance.  ...  This study was supported by Grant-in-Aid for JSPS Fellows of the Ministry of Education, Culture, Science and Technology.  ... 
doi:10.1093/ietele/e89-c.3.364 fatcat:jusu5csijbgg7c7jaef4gpfvwa

Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs

A. Koukab, K. Banerjee, M. Declercq
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The substrate noise coupling problems in today's complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers.  ...  In this paper, we propose a global methodology that includes an early verification in the design flow as well as a postlayout iterative optimization to deal with substrate noise, and helps designers to  ...  ACKNOWLEDGMENT The authors would like to thank N. Joehl, P. Favre and C. Dehollain from LEG-EPFL for helpful discussions and providing the test circuits.  ... 
doi:10.1109/tcad.2004.828117 fatcat:frcmifxfdfez3doyvenb6kes74

Measured Effectiveness of Deep N-well Substrate Isolation in a 65nm Pixel Readout Chip Prototype [article]

Peilian Liu, Maurice Garcia-Sciveres, Timon Heim, Amanda Krieger, Dario Gnani
2020 arXiv   pre-print
This study will show that the circuit with analog on the substrate and digital in deep N-well has better noise isolation between analog and digital.  ...  The same charge sensitive preamplifier and discriminator circuit with different isolation strategies has been tested to compare the isolation of both analog and digital circuits from the substrate of a  ...  Vthin1 with digital off or on, for a few selected pixels on one of our tested chips, along with straight line fits intersecting the 0.1 Hz horizontal line to extract the intercept which is called critical  ... 
arXiv:1908.06182v3 fatcat:accso6quf5epxeeulawgphtob4
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