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Ring-Oscillator Type Multi-Chip Clock Signal Synchronization Technique with In-Phase Clock Bus Lines

Kang-In Heo, Sung-Jin Kim, Hyun-Su Kim, Gyu Moon
2016 International Journal of Control and Automation  
With a few connection lines, similar to Data Bus, between two chips, named CBL (Clock Bus Line), a multi-chip synchronization method is newly proposed and proved through simulations and TTL chip measurements  ...  Generation and distribution of clock signals with minimum skews becomes a critical factor in overall system performance in today's GHz operation speed.  ...  Output Waveform of Ring Oscillator for +1% of a Voltage Difference: (A) SPICE Simulation and (B) Measurement Waveform In the same way, clock signal skews are simulated and measured with ±2% of voltage  ... 
doi:10.14257/ijca.2016.9.12.02 fatcat:wzvcow7nujd2rjq3fqkx7x6p7y

Application of the DRS4 chip for GHz waveform digitizing circuits

Hai-Bo Yang, Hong Su, Jie Kong, Ke Cheng, Jin-Da Chen, Cheng-Ming Du, Jing-Zhe Zhang
2015 Chinese Physics C, High Energy Physics & Nuclear Physics  
At present, fast waveform digitizing circuit is more and more employed in modern physics experiments for processing the signals from an array detector.  ...  The several boards can be cascaded to construct a multi-board system. The good performances make the circuit board to be used not only for physics experiments, but also for other applications.  ...  The analog frontend circuit is simulated by PSpice, the three dB bandwidth of the analog frontend is about one GHz when the load of circuit is a 10pF capacitance.  ... 
doi:10.1088/1674-1137/39/5/056101 fatcat:74tnq6ekbbfntmbsa4k3vw4g6a

Synchronous Chip-to-Chip Communication with a Multi-Chip Resonator Clock Distribution Network [article]

Jonathan Egan, Max Nielsen, Joshua Strong, Vladimir V. Talanov, Ed Rudman, Brainton Song, Quentin Herr, Anna Herr
2021 arXiv   pre-print
with a 2 GHz resonant clock.  ...  In such systems, performance of the data link between chips mounted on a multi-chip module (MCM) is a critical driver of performance.  ...  ACKNOWLEDGMENTS The authors acknowledge Andrew Brownfield for developing high frequency test setup and assisting with circuit test, and Paul Chang for assisting with data reduction and analysis.  ... 
arXiv:2109.00560v1 fatcat:jf3ib3a5tfhsbd2krolriv67cm

Picosecond optical pulse processing using a terahertz-bandwidth reconfigurable photonic integrated circuit

Yiwei Xie, Leimeng Zhuang, Arthur J. Lowery
2018 Nanophotonics  
In the experiment, we successfully verified clock rate multiplication, arbitrary waveform generation, discretely and continuously tunable delays, multi-path combining and bit-pattern recognition for 1.2  ...  Chip-scale integrated optical signal processors promise to support a multitude of signal processing functions with bandwidths beyond the limit of microelectronics.  ...  We thank LioniX International, The Netherlands, for fabricating and packaging the test chip.  ... 
doi:10.1515/nanoph-2017-0113 fatcat:ui5uvphegjeuvjzqfujjafp44m

Advanced transient waveform digitizers

Stuart Kleinfelder, Peter W. Gorham
2003 Particle Astrophysics Instrumentation  
A series of multi-channel transient waveform digitization integrated circuits with up to 5 GHz sample rates and parallel 10-bit digitization has been designed, tested, and fabricated in large quantities  ...  Acquisition sample rates range from ~50 kHz to ~3 GHz. Analog input bandwidth is approximately 350 MHz. Fixed-pattern spatial noise, after on-chip digitization, is equivalent to ~5 mV RMS.  ...  These differed from their predecessors by being capable of recording signals at multi-GHz sample rates.  ... 
doi:10.1117/12.472486 fatcat:mdcjau34jbcudfdloxy2iaftyq

RF interconnect for multi-gbit/s board-level clock distribution

Woonghwan Ryu, Junwoo Lee, Hyungsoo Kim, Seungyoung Ahn, Namhoon Kim, Baekkyu Choi, Donggun Kam, Joungho Kim
2000 IEEE Transactions on Advanced Packaging  
, especially for multi-processor systems.  ...  In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz  ...  (a) Demonstration of the generating on-chip digital clocks of up to 1.5 GHz using the RF clock and (b) waveforms measured at the input RF clocking signal, on-chip two-phase clock generated by the RF clock  ... 
doi:10.1109/6040.861553 fatcat:23cfb6xjq5hurpmr5ay5hjchae

The SST Fully-Synchronous Multi-GHz Analog Waveform Recorder with Nyquist-Rate Bandwidth and Flexible Trigger Capabilities [article]

Stuart A. Kleinfelder, Edwin Chiem, Tarun Prakash
2015 arXiv   pre-print
The design and performance of a fully-synchronous multi-GHz analog transient waveform recorder I.C. ("SST") with fast and flexible trigger capabilities is presented.  ...  Only three active control lines are necessary for operation: Reset, Start/Stop and Read-Clock.  ...  ACKNOWLEDGMENTS We thank Wei Cai for her assistance designing the SST's LVDS receiver. We also thank Steve Barwick and numerous other members of the ARIANNA collaboration for invaluable input.  ... 
arXiv:1505.07085v1 fatcat:mlivj4d3o5djzhta5hidn5xlqq

A 2.2V 200mW 3GHz Ring Oscillator Based Waveform

Xuefeng Yu, Fa Foster Dai, David J. Irwin, Richard C. Jaeger
2009 2009 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems  
This work presents a periodic arbitrary waveform generator based on a ring oscillator structure implemented in a 0.13µm SiGe BiCMOS technology.  ...  The total area of the SiGe chip is 1.0mm 2 .  ...  Army Space and Missile Defense Command for funding this project, Nat Albritton and Bill Fieselman at Amtec Corporation for business management, and Perry Tapp and Ken Gagnon at Kansas City Plant for fabrication  ... 
doi:10.1109/smic.2009.4770541 fatcat:hbg4rgnswje57dj3pmerxmg5se

An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration

Koichiro Noguchi, Makoto Nagata
2007 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Multi-channel waveform monitoring technique enhances built-in test and diagnostic capability of mixed-signal VLSI circuits.  ...  digital signal integrity in a systems-on-a-chip era.  ...  The authors would like to thank Masaki Hirata, Shin ichiro Azuma, Toshihiko Mori, Shiro Doushoh, and Hiroaki Ohkubo for helpful discussions.  ... 
doi:10.1109/tvlsi.2007.903921 fatcat:iusespuzazad7mjmhmdujsxkn4

A Wideband Sliding Correlator based Channel Sounder in 65 nm CMOS: An Evaluation Board Design [article]

Dipankar Shakya, Ting Wu, Theodore S. Rappaport
2020 arXiv   pre-print
compact channel sounder system with nanosecond time resolution capability for the detection of multipath signals in a wireless channel.  ...  These emerging applications motivate wireless communications hardware to operate with multi Gigahertz (GHz) bandwidth, at nominal costs, minimal size, and power consumption.  ...  A 7.5 GHz state-toggling capacity clock buffer is implemented as a test board based on Fig. 7 , for both the fast and slow clocks α and β in Fig. 1(c) .  ... 
arXiv:2009.13490v1 fatcat:grs2xes6yfbtditopf66yozcku

A 0.5-to-3 GHz software-defined radio receiver using sample domain signal processing

Run Chen, Hossein Hashemi
2013 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  
The chip includes a wideband frequency synthesizer, multi-phase nonoverlapping clock generation circuitry, bandgap and power supply regulators.  ...  A 0.5-to-3 GHz software-defined radio receiver leveraging Sampled Domain Signal Processing (SPSD) is demonstrated in a 65nm LP CMOS technology.  ...  INTRODUCTION Frequency allocation regulations combined with the rapid introduction of new wireless standards and applications have led to a high demand for integrated multi-mode, multi-band, and multi-standard  ... 
doi:10.1109/rfic.2013.6569592 fatcat:prjyl2gsk5ctvcfqklw5xdfixi

Isochronous Data Link Across a Superconducting Nb Flex Cable with 5 femtojoules per Bit [article]

Haitao Dai, Corey Kegerreis, Deepal Wehella Gamage, Jonathan Egan, Max Nielsen, Yuan Chen, David Tuckerman, Sherman E. Peek, Bhargav Yelamanchili, Michael Hamilton, Rabindra Das, Anna Herr (+1 others)
2021 arXiv   pre-print
Synchronous communication on chip and between chips mounted on a common board is enabled by the superconducting resonant clock/power network for RQL circuits.  ...  Measured results demonstrated correct functionality with a clock margin of 3 dB at 3.6 GHz, and with 5 fJ/bit at 4.2 K.  ...  We also acknowledge the contribution of Steve Shauck and Alex Braun for guidance with the digital design.  ... 
arXiv:2109.01808v2 fatcat:tjht2jishbgqzjcapyomdvpneu

A 4 GHz Non-Resonant Clock Driver With Inductor-Assisted Energy Return to Power Grid

M Alimadadi, S Sheikhaei, G Lemieux, S Mirabbasi, W Dunford, P Palmer
2010 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Power consumption of a multi-GHz local clock driver is reduced by returning energy stored in the clock-tree load capacitance back to the on-chip power-distribution grid.  ...  To achieve a nearly square clock waveform, the energy is transferred in a non-resonant way using an on-chip inductor in a configuration resembling a full-bridge DC-DC converter.  ...  Test Results Chip measurement results in Fig. 8 show energy savings for a clock frequency range of 2.75 to 4 GHz.  ... 
doi:10.1109/tcsi.2009.2037850 fatcat:isk6ho3ipbg5hihlghvpjx2mgu

Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration

Ruilin Wang, Cheng-kok Koh, Byunghoo Jung, William J. Chappell
2006 IEEE Custom Integrated Circuits Conference 2006  
We propose a novel traveling-wave oscillator (R 2 TWO) that uses reflection and regeneration of waves on a transmission line to generate multi-GHz square wave signals.  ...  Measurement results of a TSMC 0.18µm CMOS test chip show that it can generate and distribute near full-swing 6.5GHz global clock signals with power saving of more than 75% (compared with a traditional  ...  distribution of multi-GHz global clocks.  ... 
doi:10.1109/cicc.2006.320996 dblp:conf/cicc/WangKJC06 fatcat:25uj7xu67ncojnhcqxgilvd6ki

An all-digital duty-cycle and phase-skew correction circuit for QDR DRAMs

Jeong Cho, Young-Jae Min
2018 IEICE Electronics Express  
A compact all-digital duty-cycle and phase-skew correction circuit for quadrature data rate interface-based DRAM applications is presented.  ...  The measured duty-cycle error and phase-skew are below ²1% and ²5 ps, respectively.  ...  The use of rising and falling edge of a multi-phase clock signal can be one of the solutions [1] .  ... 
doi:10.1587/elex.15.20180331 fatcat:2wizvq3as5cc5enisggen2j7bi
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