Filters








2,829 Hits in 3.0 sec

Thermal Aware Buffer Insertion in the Early Stage of Physical Designs

Jaehwan Kim, Byung-Gyu Ahn, Minbeom Kim, Jongwha Chong
2012 JSTS Journal of Semiconductor Technology and Science  
Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip.  ...  The error rates are measured by SPICE simulation results.  ...  Contrast to the original delay calculation, proposed one is a type of distributed RC model to include the thermal effects on a chip, i.e. resistances of wires and cells are recalculated based on (3), so  ... 
doi:10.5573/jsts.2012.12.4.397 fatcat:r34jtqlqfbf4jfyu2vqhhplocy

A thin film thermoelectric cooler for Chip-on-Board assembly

Shiho Kim, Hyunju Lee, Namjae Kim, Jungho Yoo
2010 IEICE Electronics Express  
The proposed structure of COB cooler was modeled by electrical equivalent circuit for SPICE simulation including operational heat generation of chip and PWM control of input power supply.  ...  We have proposed and demonstrated an embedded thin film thermoelectric cooler attached between die chip and metal plate for Chip-on-Board (COB) direct assembly.  ...  Fig. 3 . 3 (a) SPICE equivalent circuit model of proposed TF TEC, (b) Measured and simulated temperature of chip die and heat spreader versus input current of TEC, (c) SPICE equivalent circuit model of  ... 
doi:10.1587/elex.7.1615 fatcat:fgrkgzm4lndahj77cbwfcxyewe

Simulation of thermal behavior for Networks-on-Chip

Tim Wegner, Claas Cornelius, Martin Gag, Andreas Tockhorn, Adelinde Uhrmacher
2010 NORCHIP 2010  
Hence, in this paper VulcaNoCs, a SystemC-based simulation environment for systems based on NoCs, is introduced.  ...  To verify the temperature model, VulcaNoCs is compared to a more commonly used SPICE-based approach, exhibiting significant increases in simulation performance of up to 98,5 % for modeling a 2×2 NoC, for  ...  In [10] Liu et al. generate a SPICE netlist in order to model the equivalent thermal RCnetwork of a chip on the granularity level of standard cells for application in thermal-aware placement and scheduling  ... 
doi:10.1109/norchip.2010.5669472 fatcat:7lzc4dv5xbedzfp762cvakhio4

Luminaire Digital Design Flow with Multi-Domain Digital Twins of LEDs

Genevieve Martin, Christophe Marty, Robin Bornoff, Andras Poppe, Grigory Onushkin, Marta Rencz, Joan Yu
2019 Energies  
The Delphi4LED European project aimed at developing multi-domain compact models of LED (for a consistent, combined description of electronic, thermal, and optical properties of LEDs) as digital twins of  ...  design for assessing design choices like e.g., number and type of LEDs versus electrical/thermal conditions and constraints, in a tool agnostic manner.  ...  of the built-in diode model of generic Spice solvers, on the one hand; while on the other hand, a new Spice-like LED model has also been proposed that is more closely based on the physics of today's heterojunction  ... 
doi:10.3390/en12122389 fatcat:6c4hff5glzgkxfox4huqzuphzy

High-temperature validated SiC power MOSFET model for flexible robustness analysis of multi-chip structures

M. Riccio, V. d'Alessandro, G. Romano, L. Maresca, G. Breglio, A. Irace, A. Castellazzi
2018 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)  
The proposed analysis, based on SPICE electrothermal Monte Carlo simulations, is then aimed to improve the design of high current systems with multi-chip devices.  ...  To this purpose, a reliable temperaturedependent SPICE model is calibrated on static and dynamic experimental curves of 1.2kV-36A commercial SiC MOSFET.  ...  The statistical fluctuations of threshold voltage and on-resistance have been evaluated on 20 devices, and a Gaussian fitting was used to perform SPICE electro-thermal Monte Carlo simulations.  ... 
doi:10.1109/ispsd.2018.8393698 fatcat:2tgmns4m35dljf3wczcoasmqsq

Improvement of microsystem throughput using new cooling system

Adama Samake, Piotr Kocanda, Andrzej Kos
2016 Scientific Journals of Rzeszów University of Technology Series Electrotechnics  
Based on this assumption, the authors compute the TS value versus different parameters using RC thermal compact model in Spice environment.  ...  The analogy between thermal and electrical parameters allows to model RC thermal compact model of structure (chip fixed to the cooling system).  ...  The thermal compact model based on analogy between thermal and electrical paramerters enables the observation of time shift scenario in electronic systems.  ... 
doi:10.7862/re.2016.1 fatcat:3c4zfj2qv5avra2exjse6jbzgy

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring

Maria Malits, Igor Brouk, Yael Nemirovsky
2018 Sensors  
It is shown that the MOSFET threshold voltage (V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit.  ...  This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology.  ...  The help of Ida Shumpei from Murata in the transient simulations is highly appreciated. Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/s18051629 pmid:29783742 pmcid:PMC5982330 fatcat:f53ok6cq3jhbpkccsisg5nrrha

A new reliability evaluation methodology and its application to network-on-chip routers

Hamed S. Kia, Cristinel Ababei
2012 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)  
The proposed methodology is based on a divide and conquer approach, which enjoys the benefits of device level accuracy and of block level efficiency.  ...  As a case study, we demonstrate how the proposed reliability evaluation technique can be applied to a Network-on-Chip router to identify the most vulnerable subblocks, which represent the reliability bottlenecks  ...  Another, more recent, class of reliability evaluation approaches are based on Spice simulations.  ... 
doi:10.1109/vlsi-soc.2012.7332112 fatcat:zaueiub7angw3jxaviusjbz2ju

A new reliability evaluation methodology and its application to network-on-chip routers

Hamed S. Kia, Cristinel Ababei
2012 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)  
The proposed methodology is based on a divide and conquer approach, which enjoys the benefits of device level accuracy and of block level efficiency.  ...  As a case study, we demonstrate how the proposed reliability evaluation technique can be applied to a Network-on-Chip router to identify the most vulnerable subblocks, which represent the reliability bottlenecks  ...  Another, more recent, class of reliability evaluation approaches are based on Spice simulations.  ... 
doi:10.1109/vlsi-soc.2012.6379041 dblp:conf/vlsi/KiaA12 fatcat:473pf7rrujbynevokfw5cm7sl4

A clustering technique for fast electrothermal analysis of on-chip power distribution networks

A. Magnani, M. de Magistris, A. Maffucci, A. Todri-Sanial
2016 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI)  
In [10] the Authors have proposed a novel model-order reduction technique based on the concept of node clustering.  ...  The HSPICE simulation on the reduced circuit took 6.2s. V.  ... 
doi:10.1109/sapiw.2016.7496292 fatcat:ryfydwdlabc4laxkc2zo3ruave

INVESTIGATION OF HEAT TRANSFER IN INTEGRATED CIRCUITS

Maciej Frankiewicz, Adam Gołda, Andrzej Kos
2014 Metrology and Measurement Systems  
The influence of this effect on the operation of an integrated circuit is described. The phenomenon is explained using thermal analogy implemented in the Spice environment by an R-C thermal model.  ...  Results from the model are verified by some measurements with a chip designed in CMOS 0.7 μm (5 V) technology.  ...  Next sections will describe a Spice model created to illustrate the thermal inertia phenomenon. The thermal model [5] is based on well-known analogy between thermal and electrical parameters.  ... 
doi:10.2478/mms-2014-0011 fatcat:spvpwdaiijbcpfz3ubjbr37gpm

On-chip thermal engineering for peta-scale integration

Sung-Mo (Steve) Kang
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
Computer-aided design of OI systems using novel compact models for laser diodes and photodetectors should become as routine as the current VLSI design practice that relies on SPICE-like simulation tools  ...  Optical interconnects (OI) on chip or chip-to-chip has been discussed over the last few decades. And its commercial applications have been slow in coming.  ...  Computer-aided design of OI systems using novel compact models for laser diodes and photodetectors should become as routine as the current VLSI design practice that relies on SPICE-like simulation tools  ... 
doi:10.1145/505388.505407 dblp:conf/ispd/Kang02 fatcat:yfvqj5juybbm3p2ykj6pmu2zfq

Multi-Domain Modelling of LEDs for Supporting Virtual Prototyping of Luminaires

Poppe, Farkas, Gaál, Hantos, Hegedüs, Rencz
2019 Energies  
models representing the LED chips' thermal environment in a luminaire.  ...  The first model is a semi analytical, quasi black-box model that can be implemented on the basis of the built-in diode models of spice-like circuit simulators and a few added controlled sources.  ...  This model was based on formulae widely used in textbooks and built-in diode models of the Spice-like circuit simulator.  ... 
doi:10.3390/en12101909 fatcat:bdbqaunbw5e6pi7ugqwcfmmpve

Post-packaging simulation based on MOSFET characteristics variations due to resin-molded encapsulation

Naohiro UEDA, Hirobumi WATANABE
2020 IEICE transactions on electronics  
Based on the stress distribution chart and the stress sensitivity characteristics, SNG modifies the SPICE model parameters in the target netlist according to the impact of the packaging-induced stress.  ...  The developed method is based on the stress distribution chart for the target integrated circuit (IC) and the stress sensitivity characteristics of individual devices.  ...  Based on the stress distribution chart and stress sensitivity characteristics, SNG modifies the SPICE model parameters in the target netlist according to the impact of stress intensity.  ... 
doi:10.1587/transele.2019ecp5038 fatcat:3z36i6mqu5effpys4zvh66tlsq

Closed-loop modeling of power and temperature profiles of FPGAs

Kanupriya Gulati, Sunil P. Khatri, Peng Li
2009 Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '09  
Our CAD framework accurately models the total power consumption of the design at a given temperature, finds the thermal profile of the IC under this power consumption, and then uses this new thermal information  ...  The average (maximum) error of our temperature estimates has been found to be within 1% (2.5%) compared to a full-chip 3D temperature modeling tool.  ...  are modeled in the thermal simulation.  ... 
doi:10.1145/1508128.1508207 dblp:conf/fpga/GulatiKL09 fatcat:xd54t3olm5cetf5mxot5vz4fke
« Previous Showing results 1 — 15 out of 2,829 results