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High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

Hai Wang, Min Zhang, Yan Liu
2017 Applied Sciences  
This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay.  ...  What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip.  ...  This paper uses a coarse and fine delay line to increase the dynamic range.  ... 
doi:10.3390/app7010052 fatcat:otsbhfxuevadrlczlr5eyi7zrm

New Design-methodology of High-performance TDC on a Low Cost FPGA Targets

Foudil Dadouche, Timothé Turko, Wilfried Uhring, Imane Malass, Norbert Dumas, Jean-Pierre Le Normand
2015 Sensors & Transducers  
The resolution of 42 ps as well as the INL, DNL and mean Jitter values (22 ps rms, 13 ps rms and 26 ps rms, respectively) obtained using a low cost FPGA target Cyclone family are very promising and suitable  ...  This work aims to introduce a design methodology of Time-to-Digital Converters (TDCs) on low cost Field-Programmable Gate Array (FPGA) targets.  ...  The periodic behavior of the jitter is due to the transition between two stages of the tapped delay line.  ... 
doaj:b48d20cb8f8f40c98fe90e956c5572fe fatcat:ucivqi4ningrxhvum4bdgqjhui

Review of methods for time interval measurements with picosecond resolution

Józef Kalisz
2003 Metrologia  
delay lines, and interpolation methods.  ...  Special attention has been paid to converters utilizing integrated delay lines for digital conversion of TIs, including designs with phase-locked loop and delay-locked loop circuits.  ...  A conceptually simple method of TI measurement is based on the use of the tapped delay line.  ... 
doi:10.1088/0026-1394/41/1/004 fatcat:3zipvqtr4bgi5nxstaih254ufe

A Clock Synchronizer for Repeaterless Low Swing On-Chip Links [article]

Naveen Kadayinti and Maryam Shojaei Baghini and Dinesh K. Sharma
2015 arXiv   pre-print
The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is picked by a phase detector loop.  ...  A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper.  ...  For testing the receiver's phase tracking, the transmitter's clock is deliberately shifted using an inverter based delay line, with a programmable tap.  ... 
arXiv:1510.04241v1 fatcat:vbbvctll7fhtriz4ub5jyl52fy

Programmable delay controller allowing frequency synthesis and arbitrary binary waveform generation

Marek Peca, Michael Vacek, Vojtech Michalek
2013 2013 Joint European Frequency and Time Forum & International Frequency Control Symposium (EFTF/IFC)  
Although PDC is a common digital block nowadays, the possibility to use it for low-jitter arbitrary frequency generation constrained only by minimum edge-to-edge time still seems to be uncovered.  ...  The overall output signal jitter is composed solely of the jitter of input signal and propagation jitter of the delay elements (σmax = 4.1 ps RMS).  ...  Although PDC is a common digital block nowadays, the possibility to use it for low-jitter arbitrary frequency generation still seems to be uncovered.  ... 
doi:10.1109/eftf-ifc.2013.6702147 fatcat:tyqexusy5rf3xpmdlx2ttuskqu

MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution

Joan Mauricio, Lluís Freixas, Andreu Sanuy, Sergio Gómez, Rafel Manera, Jesús Marín, Jose M. Pérez, Eduardo Picatoste, Pedro Rato, David Sánchez, Anand Sanmukh, Oscar Vela (+1 others)
2021 Electronics  
paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter  ...  The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages  ...  FPGA TDCs use the fastest delay element (typically the carry logic circuitry) in the device to use it as a Tapped Delay Line (TDL), while ASIC TDCs can be customized for a given purpose.  ... 
doi:10.3390/electronics10151816 fatcat:7br7bqi6hfadnnapiz4som2lzy

A 17ps time-to-digital converter implemented in 65nm FPGA technology

Claudio Favi, Edoardo Charbon
2009 Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '09  
The TDC comprises a coarse time discriminator and a fine delay line, capable of sustained operation at a clock frequency of 300MHz.  ...  The TDCs proposed in this paper can be compensated for process, voltage, and temperature (PVT) variations using a conventional charge pump based feedback or a digital calibration technique.  ...  The stop signal of our design is generated on board by a low jitter frequency synthesiser.  ... 
doi:10.1145/1508128.1508145 dblp:conf/fpga/FaviC09 fatcat:a3ba4m4cnvbvrgp2fuuckctqzu

A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix

Min Zhang, Hai Wang, Yan Liu
2017 Sensors  
In this paper, a high-resolution time-to-digital converter (TDC) based on a field programmable gate array (FPGA) device is proposed and tested.  ...  Benefitting from the FPGA platform, the proposed TDC has superiorities in easy implementation, low cost, and short development time.  ...  line Tapped delay line CARRY delay line Tapped delay line Tapped delay line Processing Technology 65 nm 90 nm 65 nm 0.15 µm 65 nm 90 nm 40 nm 28 nm Number of Bins 1024 200  ... 
doi:10.3390/s17040865 pmid:28420121 pmcid:PMC5424742 fatcat:sc6mgwzamralzatif5diqib454

Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier

A. N. M. Alahmadi, G. Russell, A. Yakovlev
2012 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)  
To address these issue 'on-chip' time measurement circuits have been developed in a similar way that built in self-test (BIST) evolved for 'on-chip' logic testing.  ...  The time amplifier was then connected to a 32-stage tapped delay line to create a reconfigurable time measurement circuit with an adjustable resolution range from 15 down to 0.5 ps and a dynamic range  ...  Combination of coarse and fine delay Tapped delay line + vernier delay line [8] . Digital. 10 ps. 1200 ps. Depends on the buffer delay + propagation delay of DFF. Coarse VO + Fine VO [7] .  ... 
doi:10.1109/ddecs.2012.6219089 dblp:conf/ddecs/AlahmadiRY12 fatcat:dfok75dx7jawvlz6zxwmb56mxa

Design of a High Resolution TDC Based on Multi-channel

Qingsong Zhang, Guanghui Xu, Na Li
2019 IOP Conference Series: Materials Science and Engineering  
In this paper ,a high precision time digital converter (TDC) system is designed based on Xilinx 7 series FPGA chip, which includes fine time measurement module, logic control module, rough count module  ...  A delay chain consisting of 64 fast carry chains (CARRY4) is constructed by using the CARRY4 module inherent in the chip.  ...  Therefore, the tapped delay line structure is selected in this paper,and the mainstream Xilinx tool(Vivado) is used to realize the TDC system in the 7-series FPGA chip.  ... 
doi:10.1088/1757-899x/569/3/032008 fatcat:pyspqk4cxnaovnj2mphfqbe4gy

A jitter characterization system using a component-invariant Vernier delay line

A.H. Chan, G.W. Roberts
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Time domain jitter measurement on a data signal with subgate timing resolution can be achieved using two delay chains feeding into the clock and datalines of a series of D-latches known as a Vernier delay  ...  Index Terms-Characterization , component-invariant, frequency, jitter, measurement, register transfer level (RTL), synthesizable, time, vernier delay line (VDL).  ...  For a jitter measurement, in particular, an on-chip circuit consisting of a ring oscillator and a calibration circuit was reported in [5] capable of measuring timing jitter with a resolution as low as  ... 
doi:10.1109/tvlsi.2003.820531 fatcat:di2jx4uxtrbyfhehws5j5ornhy

A 26 ps RMS time-to-digital converter core for Spartan-6 FPGAs [article]

Sebastien Bourdeauducq
2013 arXiv   pre-print
effects on the delay line.  ...  The startup calibration uses a statistical method to estimate the delay between the taps of the delay line and helps eliminate the effect of process variations.  ...  Offline calibration At startup, the core sends random pulses into the delay line (coming from a on-chip ring oscillator), builds the histogram, computes the delays (as explained in [2] ), and initializes  ... 
arXiv:1303.6840v1 fatcat:ngmj6pt2rvbr3pohskojdnubpi

A Sub-100 μm-Range-Resolution Time-of-Flight Range Image Sensor With Three-Tap Lock-In Pixels, Non-Overlapping Gate Clock, and Reference Plane Sampling

Keita Yasutomi, Yushi Okura, Keiichiro Kagawa, Shoji Kawahito
2019 IEEE Journal of Solid-State Circuits  
The range imager employs a TOF measurement technique that uses an impulse photocurrent response and a three-tap lock-in pixel based on the lateral electric field modulation.  ...  In noisy columns, jitter that acts as random telegraph noise (RTN) is observed.  ...  ACKNOWLEDGMENT The authors would like to thank DB HiTek for chip fabrication. They would also like to thank M. Tamaya at Pulstec Industrial Co., Ltd., for helpful discussion in 3-D measurement.  ... 
doi:10.1109/jssc.2019.2916310 fatcat:julj74puefhznajksnsyvxc7uu

A Low Nonlinearity, Missing-Code Free Time-to-Digital Converter Based on 28-nm FPGAs With Embedded Bin-Width Calibrations

Haochang Chen, Yongliang Zhang, David Day-Uei Li
2017 IEEE Transactions on Instrumentation and Measurement  
A low nonlinearity, missing-code free time-to-digital converter based on 28nm FPGAs with embedded bin-width calibrations. IEEE Transactions on Instrumentation and Measurement, 66 (7).  ...  The delay of each tap in the IDELAYE2 was continuously calibrated by an IDELAYCTRL module based on a low jitter reference clock.  ...  The bin-width calibration method was tested and discussed as well. Two independent low-jitter crystal oscillators (DSC1103) were used as the signal sources for code density tests.  ... 
doi:10.1109/tim.2017.2663498 fatcat:vevwjljuijemhmxhynrk7f3mga

A Highly Linear and Flexible FPGA-Based Time-to-Digital Converter [article]

Yuanyuan Hua, Danial Chitnis
2021 arXiv   pre-print
We propose a novel TDC with a single delay line and without compensation to realize a highly linear TDC by encoding the states of the delay lines instead of the thermometer code used in the conventional  ...  In order to eliminate empty histogram bins and achieve a higher level of linearity, FPGA-based TDCs typically apply compensation methods either using multiple delay lines consuming more resources or post-processing  ...  Vernier delay lines (VDLs) and Tapped Delay Lines (TDLs) are the main architectures used in the Digital TDC [20] , [27] , [28] .  ... 
arXiv:2107.13053v4 fatcat:wd4mcsjenfgmhcf5puszo3pkoi
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