Filters








6,603 Hits in 5.0 sec

Formulating Model Verification Tasks Prover-Independently as UML Diagrams [chapter]

Martin Gogolla, Frank Hilken, Philipp Niemann, Robert Wille
2017 Lecture Notes in Computer Science  
The success of Model-Driven Engineering (MDE) relies on the quality of the employed models. Thus, quality assurance through validation and verification has a tradition within MDE.  ...  We propose to formulate verifications tasks in terms of the used modeling language itself, e.g. with UML and OCL.  ...  So far UML diagrams in combination with OCL expressions have not been used as a means for formulating dedicated structural and behavioral verification tasks.  ... 
doi:10.1007/978-3-319-61482-3_14 fatcat:vpw44lrvfvactdwt2so7a2gmna

Analysis and Formal Modeling of Systems Behavior Using UML/Event-B

Kenza Kraibi, Institut de Recherche Technologique Railenium, F-59300, Famars, France, Rahma Ben Ayed, Simon Collard-Dutilleul, Philippe Bon, Dorian PEIT
2019 Journal of Communications  
This paper presents an approach combining UML and Event-B. In fact, we focus in this work on modeling the systems behavior with the joint use of some UML behavioral diagrams.  ...  The UML models are then translated into Event-B models for the systems validation as well as the verification of safety properties using B tools.  ...  ACKNOWLEDGMENT This work is supported by PRESCOM (Global safety proofs for modular design/PREuves de Sé curité globale pour la COnception Modulaire) as a part of IRT Railenium projects in collaboration  ... 
doi:10.12720/jcm.14.10.980-986 fatcat:avxiam3tdfdzhbqrwutzpwwnaa

Modeling Legislation by using UML State Machine Diagrams

Vjeran Strahonja
2006 2006 Canadian Conference on Electrical and Computer Engineering  
Business oriented behavioral models of legislation enable to understand the system better, support the detection of anomalies and help to improve the quality of legislation by validation and verification  ...  More specific, this paper presents a static analysis approach to the checking of correctness and consistency of the UML state machine diagrams specifications of legislation.  ...  and refactoring) 2) Transformation to UML constructs and representation in a form of diagrams 3) Validation and verification (detection of anomalies based on static and dynamic analysis) 4) Improvement  ... 
doi:10.1109/ccece.2006.277286 dblp:conf/ccece/Strahonja06 fatcat:uqfuhvskirgfdhq6vs3ykagpvu

USMMC: a self-contained model checker for UML state machines

Shuang Liu, Yang Liu, Jun Sun, Manchun Zheng, Bimlesh Wadhwa, Jin Song Dong
2013 Proceedings of the 2013 9th Joint Meeting on Foundations of Software Engineering - ESEC/FSE 2013  
Tool support for verification UML designs can also encourage consistent usage of UML diagrams throughout the software development procedure.  ...  The evaluation results show the effectiveness and scalability of our tool.  ...  flaws in early stages into practice, rigorous analysis and verification supports on the UML diagrams are necessary.  ... 
doi:10.1145/2491411.2494595 dblp:conf/sigsoft/LiuL0ZWD13 fatcat:xmv7f7kwqvdjtpc7bwsloblu4y

An Spin / Promela Application for Model checking UML Sequence Diagrams

Cristian L. Vidal-Silva, Rodolfo Villarroel, Jos´e Rubio, Franklin Johnson, Erika Madariaga, Camilo Campos, Luis Carter
2018 International Journal of Advanced Computer Science and Applications  
UML sequence diagrams usually represent the behavior of systems execution.  ...  UML sequence diagrams applications are often on the requirement and design phases of the software development process, and their correctness guarantees the accurate and transparent implementation of software  ...  Automated verification of UML sequence diagrams' correctness is necessary because they can model critical algorithmic behaviors of information systems.  ... 
doi:10.14569/ijacsa.2018.091071 fatcat:liikcuxwvreppktgey6ipctvx4

Formalization of UML use case diagram-a Z notation based approach

Sabnam Sengupta, Swapan Bhattacharya
2006 2006 International Conference on Computing & Informatics  
Development of a tool based on this approach will produce a visual representation of a formalized UML use case diagram, from which automated traceability and verification of the design phase can be achieved  ...  Therefore, it is not possible to automate the verification of tracking requirements captured in a use case diagram in the design phase.  ...  In this paper, we propose to formalize UML use case diagram based on which automated traceability and verification in the design phase can be achieved. III.  ... 
doi:10.1109/icoci.2006.5276507 fatcat:swi5t3bm5nghxnvhlichsoxj2q

Transformation of UML Behavioral Diagrams to Support Software Model Checking

Luciana Brasil Rebelo dos Santos, Valdivino Alexandre de Santiago, Nandamudi Lankalapalli Vijaykumar
2014 Electronic Proceedings in Theoretical Computer Science  
behavior and structure of the software.  ...  Verification and Validation of complex software developed according to UML is not trivial due to complexity of the software itself, and the several different UML models/diagrams that can be used to model  ...  [3] seems to require an assorted number of diagrams (structural, behavioral and time diagrams), which are not always available on the documentation.  ... 
doi:10.4204/eptcs.147.10 fatcat:kayselsdyndr5gkzoosymzgeli

A tool for automatic UML model consistency checking

Jocelyn Simmonds, M. Cecilia Bastarrica
2005 Proceedings of the 20th IEEE/ACM international Conference on Automated software engineering - ASE '05  
(CFd04) Component diagrams UML Profile Our approach • Formalise UML using Description Logics (DL) • Offer a uniform verification for the widest possible range of consistency problems • ∼ jsimmond  ...  to express UML (CCDGL02) • existence of optimised DL reasoning engines • reasoning engines offer query lan- guages CONS • reasoning on UML models is EXPTIME-hard (but the UML metamodel is  ... 
doi:10.1145/1101908.1101989 dblp:conf/kbse/SimmondsB05 fatcat:wantgebozramnb23fimjnsxay4

Automatic generation of PROMELA code from sequence diagram with imbricate combined fragments

Abdelkrim Amirat, Ahcen Menasria, Mouna Ait Oubelli, Nadia Younsi
2012 Second International Conference on the Innovative Computing Technology (INTECH 2012)  
Formal verification of UML diagram is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal  ...  The most widely used techniques for system or software verification: Simulation and testing, deductive verification and Model checking.  ...  Related Work Several researchers have studied the Verification and Validation of UML diagrams [1, 2, 3] and in particular, an approach for the formal verification of UML diagrams, such as class, state  ... 
doi:10.1109/intech.2012.6457780 fatcat:4eq2bue6rvbhbirges5acbdq4i

Verification of the Correctness in Composed UML Behavioural Diagrams [chapter]

Samir Ouchani, Otmane Ait Mohamed, Mourad Debbabi, Makan Pourzandi
2010 Studies in Computational Intelligence  
In this paper, a verification methodology of a composition of UML behavioural diagrams (State Machine, Activity Diagram, and Sequence Diagram) is proposed.  ...  This operator provides an elegant way to define the combination of different kind of UML diagrams.  ...  At the beginning of the verification part, we have a set of separated UML behavioral diagrams, for this reason we have to extract their corresponding semantic models (CTS) separately, and based on their  ... 
doi:10.1007/978-3-642-13273-5_11 fatcat:bqr4g347nvdkhlnizwri4io6bq

Validation: Conceptual versus Activity Diagram Approaches

Sabah Al-Fedaghi
2021 International Journal of Advanced Computer Science and Applications  
In UML specifications, validation verifies the correctness of UML diagrams against any constraints and rules defined within the model.  ...  This paper focuses on the notion of validation using activity diagrams and contrasts that process with a proposed method that involves an informal validation procedure.  ...  One of the goals of the Foundational UML Subset (fUML [12] ) is to provide a well-defined execution of UML activity diagrams.  ... 
doi:10.14569/ijacsa.2021.0120632 fatcat:uwci6vmdbja5vddjbm6pjk7zuy

Design validation of embedded dependable systems

A. Bondavalli, A. Fantechi, D. Latella, L. Simoncini
2001 IEEE Micro  
These requirements would include environmental, legal, and ethical considerations. • The evolution and verification of product and process designs.  ...  The quality of a product design depends on the quality of the process that produces it.  ...  Fault injection use had two main objectives: • to complement the formal verification of mechanisms, which made behavioral and structural abstractions on the failure mode assumptions; and • to support the  ... 
doi:10.1109/40.958699 fatcat:wghik64werc27lhq3tyumg2xn4

Modeling Behavior with Interaction Diagrams in a UML and OCL Tool [chapter]

Martin Gogolla, Lars Hamann, Frank Hilken, Matthias Sedlmeier
2015 Lecture Notes in Computer Science  
This paper discusses system modeling with UML behavior diagrams. We consider statecharts and both kinds of interaction diagrams, i.e., sequence and communication diagrams.  ...  We assess the introduced features and propose selection mechanisms which should be available in both kinds of interaction diagrams.  ...  USE claims to be useful for validation and verification of UML and OCL models.  ... 
doi:10.1007/978-3-319-21912-7_2 fatcat:pld67bhkqrezjj6y7xhll56ecq

Verifying dynamic aspects of UML models

M Soeken, R Wille, R Drechsler
2011 2011 Design, Automation & Test in Europe  
However, most of them focus only on the static view of a UML model. In this paper, an automatic approach is presented which checks verification tasks for dynamic aspects of a UML model.  ...  The underlying verification problem is encoded as an instance of the satisfiability problem and subsequently solved using a SAT Modulo Theory solver.  ...  A class diagram comprises a UML model, which can be used e.g. to describe the structure of a system. An instantiation of a UML model is called a system state and is visualized by an object diagram.  ... 
doi:10.1109/date.2011.5763177 dblp:conf/date/SoekenWD11 fatcat:65pqrogxnveerilbrhzqkcwdd4

Formal Verification for Embedded Systems Design Based on MDE [chapter]

Francisco Assis Moreira do Nascimento, Marcio Ferreira da Silva Oliveira, Flávio Rech Wagner
2009 IFIP Advances in Information and Communication Technology  
By means of transformations on the UML model of the embedded system, a MOF-based representation for the network of timed automata is automatically obtained, which can be used as input to formal verification  ...  class and sequence diagrams.  ...  Acknowledgements This work described herein was partly supported by the German Ministry for Education and Research (BMBF) through the ITEA2 project TIMMO (01IS07002).  ... 
doi:10.1007/978-3-642-04284-3_15 fatcat:c7wuenfpurdezhcjeqqdwirwwq
« Previous Showing results 1 — 15 out of 6,603 results