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Architectural considerations for application-specific counterflow pipelines

B.R. Childers, J.W. Davidson
1999 Proceedings 20th Anniversary Conference on Advanced Research in VLSI  
Sutherland, Sproull, and Molnar have proposed a new pipeline organization called the Counterflow Pipeline (CFP).  ...  An innovative computer organization called the Counterflow Pipeline (CFP), proposed by Sproull, Sutherland, and Molnar [27], has several characteristics that make it an ideal target organization for the  ...  Sproull, Sutherland, and Molnar give a more detailed description of CFP's [27] . The counterflow pipeline has two pipelines flowing in opposite directions. One is the instruction pipeline.  ... 
doi:10.1109/arvlsi.1999.756034 dblp:conf/arvlsi/ChildersD99 fatcat:sm2hu2vhrvghjeifj2ca3p7zem

Counterflow pipelining

Manoj Ampalam, Montek Singh
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
For the efficient implementation of the new architectural features, a radically new approach inspired by Sproull's counterflow pipelines [7] is proposed.  ...  The net impact is a significant improvement in the throughput of a certain class of systems-e.g., those involving conditional computation-where a bottleneck pipeline stage can often be preempted if its  ...  The notion of counterflow was first introduced by Sproull et al. for the design of the Sun Counterflow Pipeline Processor [7] .  ... 
doi:10.1145/1233501.1233627 dblp:conf/iccad/AmpalamS06 fatcat:uhdzr67mlfcpvd4ejaf24l7y44

Counterflow Pipelining: Architectural Support for Preemption in Asynchronous Systems using Anti-Tokens

Manoj Ampalam, Montek Singh
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
For the efficient implementation of the new architectural features, a radically new approach inspired by Sproull's counterflow pipelines [7] is proposed.  ...  The net impact is a significant improvement in the throughput of a certain class of systems-e.g., those involving conditional computation-where a bottleneck pipeline stage can often be preempted if its  ...  The notion of counterflow was first introduced by Sproull et al. for the design of the Sun Counterflow Pipeline Processor [7] .  ... 
doi:10.1109/iccad.2006.320024 fatcat:7jh36c3rvvgkxgvbdk4bkvtaki

Custom wide counterflow pipelines for high-performance embedded applications

B.R. Childers, J.W. Davidson
2004 IEEE transactions on computers  
Sutherland, Sproull, and Molnar originally proposed a processor organization called the counterflow pipeline (CFP) as a general-purpose architecture.  ...  Using an analytic cost model, we show that custom WCFPs do not unduly increase the cost of the original counterflow pipeline architecture, yet they retain the simplicity of the CFP.  ...  ACKNOWLEDGMENTS The authors would like to thank the reviewers for their careful reading and helpful comments on the initial manuscript.  ... 
doi:10.1109/tc.2004.1261825 fatcat:pswfmrtejjglxcwtnfoanf4m7q

Asynchronous processor survey

T. Werner, V. Akella
1997 Computer  
Synchronous processors, dependent on a clock, are not necessarily the perfect computing solution.  ...  Furthermore, asynchronous processors may yet prove to offer reduced power dissipation by inherently shutting down unused portions of the circuit.  ...  CFPP-Counterflow Pipeline Processor The CFPP was developed in 1994 at Sun Microsystems by Ivan Sutherland, Robert Sproull, and Charles Molnar. 8 In this architecture, as instructions flow through the  ... 
doi:10.1109/2.634866 fatcat:spusik5cybc2hox7hqrzjjbjju

A counterflow pipeline experiment

B. Coates, J. Ebergen, J. Lexau, S. Fairbanks, I. Jones, A. Ridgway, D. Harris, I. Sutherland
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems  
The maximum total throughput of the chip, which is the sum of the throughputs of the two pipelines, varies between 491 MDI/s (Mega Data Items per second) and 699 MDI/s, depending on the amount of interaction  ...  The counterflow pipeline architecture [12] consists of two interacting pipelines in which data items flow in opposite directions. Interactions occur between two items when they meet in a stage.  ...  We thank Wes Clark for his numerous and valuable comments on an earlier draft of this paper.  ... 
doi:10.1109/async.1999.761531 dblp:conf/async/CoatesELFJRHS99 fatcat:tmpcmogwk5c7dmjxtydvsu64em

Custom wide counterflow pipelines for high performance embedded applications

B.R. Childers, J.W. Davidson
Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)  
Sutherland, Sproull, and Molnar originally proposed a processor organization called the counterflow pipeline (CFP) as a general-purpose architecture.  ...  Using an analytic cost model, we show that custom WCFPs do not unduly increase the cost of the original counterflow pipeline architecture, yet they retain the simplicity of the CFP.  ...  ACKNOWLEDGMENTS The authors would like to thank the reviewers for their careful reading and helpful comments on the initial manuscript.  ... 
doi:10.1109/pact.2000.888331 dblp:conf/IEEEpact/ChildersD00 fatcat:jclrvg6yqfcr5mebobsudswa5y

An area- and energy-efficient asynchronous booth multiplier for mobile devices

J. Hensley, A. Lastra, M. Singh
IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.  
First, a novel counterflow organization is introduced, in which the data bits flow in one direction, and the Booth commands piggyback on the acknowledgments flowing in the opposite direction.  ...  Third, our design performs overlapped execution of multiple iterations of the Booth algorithm.  ...  It must be emphasized that our counterflow pipeline organization is quite different from another counterflow organization proposed by Sproull et al. [16] .  ... 
doi:10.1109/iccd.2004.1347892 dblp:conf/iccd/HensleyLS04 fatcat:vtgc6zuvtnchvheor7pmvnsn3e

Practical advances in asynchronous design

E. Brunvand, S. Nowick, K. Yun
Proceedings International Conference on Computer Design VLSI in Computers and Processors  
The second describes a variety of approaches to asynchronous datapaths. The third section is on asynchronous and self-timed circuits applied to the design of general purpose processors  ...  This tutorial will present the current state of the art in asynchronous circuit and system design in three different areas. The first section details asynchronous control systems.  ...  Rotary Pipeline Processor The rotary pipeline processor is an architecture for superscalar computing [43] .  ... 
doi:10.1109/iccd.1997.628936 dblp:conf/iccd/BrunvandNY97 fatcat:tksdrzbvdjapfdltga7iow3qp4

Real-time merging

M.R. Greenstreet
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems  
We present two new implementations of a merge: one that uses an arbiter, and one that uses Schmitt triggers but no arbiters.  ...  Based on these designs, we explore a class of concurrent computations that can be performed in guaranteed bounded time, and we raise some new questions about what is possible in asynchronous design.  ...  The anonymous referees provided many helpful comments on an earlier draft of this paper.  ... 
doi:10.1109/async.1999.761533 dblp:conf/async/Greenstreet99 fatcat:3rboybzmzbhxnj5j3ahfinecfm

A hierarchical approach to formal modeling and verification of asynchronous circuits [article]

Cuong Kim Chau, 0000-0002-9723-9557, Austin, The University Of Texas At, Austin, The University Of Texas At, Hunt, Warren A., 1958-
2019
Specifically, we verify the functional correctness of self-timed systems in terms of relationships between their input and output sequences.  ...  The input-output relationship of a verified submodule is determined based on the communication signals at the submodule's input and output ports, while abstracting [...]  ...  Loewenstein [35] formally verified some properties of the asynchronous, Sproull counterflow pipeline processor (CFPP) architecture using the higherorder logic, HOL theorem prover [21, 22] .  ... 
doi:10.26153/tsw/2194 fatcat:gv57ebwtw5hb7aipzd5mezni6q