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Synchronization, coherence, and event ordering in multiprocessors

M. Dubois, C. Scheurich, F.A. Briggs
1988 Computer  
The instruction set of a multiprocessor usually contains basic instructions that are used to implement synchronization and communication between cooperating processes.  ...  The notions of synchronization and communication are difficult to separate because communication  ...  Acknowledgment Through many technical discussions, William Collier of IBM Poughkeepsie helped shape the content of this article.  ... 
doi:10.1109/2.15 fatcat:yflu46ikqjbbdh4tdgalpc5wmm

A design kit for a fully working shared memory multiprocessor on FPGA

Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2007 Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07  
It deals with the consistency of shared data, with no need of hardware coherence protocol, but uses a software model to properly synchronize the local copies with the shared memory image.  ...  The architecture is synthesizable with standard IPs, such as the softcores and interconnect elements, which may be found in any commercial FPGA toolset.  ...  [7] that evaluates and suggests software coherency as a solution when looking for favorable power/performance ratios, in the context of Multiprocessor System-on-Chip.  ... 
doi:10.1145/1228784.1228841 dblp:conf/glvlsi/TumeoMPFS07 fatcat:5jvrar7jnvejli4xwuvkeu567y

Architectural mechanisms for explicit communication in shared memory multiprocessors

Umakishore Ramachandran, Gautam Shah, Anand Sivasubramaniam, Aman Singla, Ivan Yanasak
1995 Proceedings of the 1995 ACM/IEEE conference on Supercomputing (CDROM) - Supercomputing '95  
The motivation stems from the observation that applications display wide diversity in terms of sharing characteristics and hence impose different communication requirements on the system.  ...  The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors.  ...  Memory Systems The design choices in realizing a cache-coherent shared memory system include the memory consistency model, the cache coherence protocol, and any explicit communication primitives.  ... 
doi:10.1145/224170.224399 dblp:conf/sc/RamachandranSSSY95 fatcat:wrdbbvjsanfe3d2sabpk3kqvbm

Lightweight DMA management mechanisms for multiprocessors on FPGA

Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2008 2008 International Conference on Application-Specific Systems, Architectures and Processors  
This interface allows to program the embedded multiprocessor architecture on FPGA with simple DMAs using the same DMA techniques adopted on high performance multiprocessors with complex DMA controllers  ...  This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each processor.  ...  Note that the data cache in MicroBlaze does not support any coherence protocol, so its implementation in a multiprocessor system requires either the development of a software mechanism to support explicit  ... 
doi:10.1109/asap.2008.4580191 dblp:conf/asap/TumeoMPFS08 fatcat:k5o3rmecb5gcjijl4ukk56bbky

Assessing Programming Costs of Explicit Memory Localization on a Large Scale Shared Memory Multiprocessor

Silvio Picano, Eugene D. Brooks III, Joseph E. Hoag
1992 Scientific Programming  
We describe the techniques used to exploit our multiprocessor (the BBN TC2000) on a network simulation program, showing the resulting performance gains and the associated programming costs.  ...  To make effective use of such an architecture, the programmer is responsible for designing the program's structure to match the underlying multiprocessors capabilities.  ...  The authors wish to thank Brent Gorda, Tammy W elcome and Linda Woods of the MPCI at LLNL and Ken Sed~ck for their assistance with the parallel programming support for the BBN multiprocessor.  ... 
doi:10.1155/1992/923069 fatcat:cjvqqrdrfvc6nggu7qhhjcrema

Integrating message-passing and shared-memory

David Kranz, Kirk Johnson, Anant Agarwal, John Kubiatowicz, Beng-Hong Lim
1993 SIGPLAN notices  
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors.  ...  While such a programming model can be implemented on both shared-memory and messagepassing architectures, we argue that the transparent, coherent caching of global data provided by many shared-memory architectures  ...  We would also like to thank Alan Mainwaring, Dave Douglas, and Thinking Machines Corporation for their generosity and assistance in porting our simulation system to the CM-5.  ... 
doi:10.1145/173284.155338 fatcat:dipn6mfrc5aupi2cwgy7jxdbdy

Integrating message-passing and shared-memory

David Kranz, Kirk Johnson, Anant Agarwal, John Kubiatowicz, Beng-Hong Lim
1993 Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPOPP '93  
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors.  ...  While such a programming model can be implemented on both shared-memory and messagepassing architectures, we argue that the transparent, coherent caching of global data provided by many shared-memory architectures  ...  We would also like to thank Alan Mainwaring, Dave Douglas, and Thinking Machines Corporation for their generosity and assistance in porting our simulation system to the CM-5.  ... 
doi:10.1145/155332.155338 dblp:conf/ppopp/KranzJAKL93 fatcat:6tjf3vkdyzgdxdkri4k6pfuw74

Integrating message-passing and shared-memory

David Kranz, Beng-Hong Lim, Kirk Johnson, John Kubiatowicz, Anant Agarwal
1993 SIGPLAN notices  
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors.  ...  While such a programming model can be implemented on both shared-memory and messagepassing architectures, we argue that the transparent, coherent caching of global data provided by many shared-memory architectures  ...  We would also like to thank Alan Mainwaring, Dave Douglas, and Thinking Machines Corporation for their generosity and assistance in porting our simulation system to the CM-5.  ... 
doi:10.1145/156668.156705 fatcat:zetpzu4x45g37nx7y6xyruli5m

Temporally silent stores

Kevin M. Lepak, Mikko H. Lipasti
2002 Tenth international conference on architectural support for programming languages and operating systems on Proceedings of the 10th international conference on architectural support for programming languages and operating systems (ASPLOS-X) - ASPLOS '02  
We redefine multiprocessor sharing to account for temporal silence and show that in the limit, up to 45% of communication misses in scientific and commercial applications can be eliminated by exploiting  ...  We describe a practical mechanism that detects temporally silent stores and removes the coherence traffic they cause in conventional multiprocessors.  ...  Acknowledgements This work was supported in part by the National Science Foundation with grants CCR-0073440, CCR-0083126, EIA-0103670, and CCR-0133437, and generous equipment donations and Fellowship support  ... 
doi:10.1145/605398.605401 fatcat:efqkivbrknd5vcrbg4ncbusa5e

Compiling for Scalable Multiprocessors with Polaris

Yunheung Paek, David A. Padua
1997 Parallel Processing Letters  
Non-cache coherent m a c hines, by contrast, allow the programmer or the compiler to have explicit and direct control over communications through explicit data movement operations.  ...  In this work, we pro t from the fact that the Cray T3D supports fast single-sided communication in the form of PUT/GET primitives.  ...  Acknowledgements We w ould like to thank the Cray Research Inc. and the Pittsburgh Supercomputing Center for granting machine times for the experiments reported in this paper.  ... 
doi:10.1142/s0129626497000413 fatcat:gta4lqs46raixl4hbppfpgbnay

Cache-coherent distributed shared memory: perspectives on its development and future challenges

J. Hennessy, M. Heinrich, A. Gupta
1999 Proceedings of the IEEE  
Cache coherence allows such architectures to use caching to take advantage of locality in applications without changing the programmer's model of memory.  ...  We review the key developments that led to the creation of cache-coherent distributed shared memory and describe the Stanford DASH Multiprocessor, the first working implementation of hardware-supported  ...  The Problem of Cache Coherence When used in a multiprocessor, caching introduces an additional problem: cache coherence , which arises when different processors cache and update values of the same memory  ... 
doi:10.1109/5.747863 fatcat:koqfmkqdibaylcxfiheb33bwly

Temporally silent stores

Kevin M. Lepak, Mikko H. Lipasti
2002 Tenth international conference on architectural support for programming languages and operating systems on Proceedings of the 10th international conference on architectural support for programming languages and operating systems (ASPLOS-X) - ASPLOS '02  
We redefine multiprocessor sharing to account for temporal silence and show that in the limit, up to 45% of communication misses in scientific and commercial applications can be eliminated by exploiting  ...  We describe a practical mechanism that detects temporally silent stores and removes the coherence traffic they cause in conventional multiprocessors.  ...  Acknowledgements This work was supported in part by the National Science Foundation with grants CCR-0073440, CCR-0083126, EIA-0103670, and CCR-0133437, and generous equipment donations and Fellowship support  ... 
doi:10.1145/605397.605401 dblp:conf/asplos/LepakL02 fatcat:sowmfg7nwze2nh62ahjlpe273m

Temporally silent stores

Kevin M. Lepak, Mikko H. Lipasti
2002 SIGPLAN notices  
We redefine multiprocessor sharing to account for temporal silence and show that in the limit, up to 45% of communication misses in scientific and commercial applications can be eliminated by exploiting  ...  We describe a practical mechanism that detects temporally silent stores and removes the coherence traffic they cause in conventional multiprocessors.  ...  Acknowledgements This work was supported in part by the National Science Foundation with grants CCR-0073440, CCR-0083126, EIA-0103670, and CCR-0133437, and generous equipment donations and Fellowship support  ... 
doi:10.1145/605432.605401 fatcat:ghkmtqxhtjgvverpi5x5buifiq

Temporally silent stores

Kevin M. Lepak, Mikko H. Lipasti
2002 ACM SIGOPS Operating Systems Review  
We redefine multiprocessor sharing to account for temporal silence and show that in the limit, up to 45% of communication misses in scientific and commercial applications can be eliminated by exploiting  ...  We describe a practical mechanism that detects temporally silent stores and removes the coherence traffic they cause in conventional multiprocessors.  ...  Acknowledgements This work was supported in part by the National Science Foundation with grants CCR-0073440, CCR-0083126, EIA-0103670, and CCR-0133437, and generous equipment donations and Fellowship support  ... 
doi:10.1145/635508.605401 fatcat:juimv5gh45ailobeaf2wajjb2q

Temporally silent stores

Kevin M. Lepak, Mikko H. Lipasti
2002 SIGARCH Computer Architecture News  
We redefine multiprocessor sharing to account for temporal silence and show that in the limit, up to 45% of communication misses in scientific and commercial applications can be eliminated by exploiting  ...  We describe a practical mechanism that detects temporally silent stores and removes the coherence traffic they cause in conventional multiprocessors.  ...  Acknowledgements This work was supported in part by the National Science Foundation with grants CCR-0073440, CCR-0083126, EIA-0103670, and CCR-0133437, and generous equipment donations and Fellowship support  ... 
doi:10.1145/635506.605401 fatcat:i4bjcgyvzjeh7l4xcxzhggnide
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