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High parallel disparity map computing on FPGA

Humberto Calderon, Jesus Ortiz, Jean-Guy Fontaine
2010 Proceedings of 2010 IEEE/ASME International Conference on Mechatronic and Embedded Systems and Applications  
The tools are selected based on the availability of the license and this paper will give a glance on the tools for the beginner. The tools are evaluated on the basis of architectural support (i.e.  ...  These HLS tools are developed by many FPGA manufacturers based on the application needs and they compete among themselves for producing the tool that supports the faster time to market of the products.  ...  Since the RTL synthesis was under the the process of parallel computing in FPGA is discussed, debate at that time and the RTL tools are not supported the tools are evaluated based on architecture and by  ... 
doi:10.1109/mesa.2010.5552049 fatcat:jilbddh7gbcpvpj5yytvrk34ga

Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs

Lech Jozwiak, Menno Lindwer
2011 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing  
This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors  ...  It is related to a European project ASAM being currently executed in the framework of the ARTEMIS program.  ...  ACKNOWLEDGMENT The authors of this paper are indebted to all partners of the ASAM project.  ... 
doi:10.1109/pdp.2011.55 dblp:conf/pdp/JozwiakL11 fatcat:s7hkhc7gx5bhtnarwpquhwvc5m

Experiencing a Problem-Based Learning Approach for Teaching Reconfigurable Architecture Design

Erwan Fabiani
2009 International Journal of Reconfigurable Computing  
The practical work sessions of this course rely on active pedagogy using problem-based learning, focused on designing a reconfigurable architecture for the implementation of an application class of image  ...  This paper presents the "reconfigurable computing" teaching part of a computer science master course (first year) on parallel architectures.  ...  Acknowledgment The author thanks Loïc Lagadec for his fruitful comments.  ... 
doi:10.1155/2009/923415 fatcat:a3mh3hwmoncjzlqeg44ybulqce

Software defined architectures for data analytics

Vito Giovanni Castellana, Marco Minutoli, Antonino Tumeo, Marco Lattuada, Pietro Fezzardi, Fabrizio Ferrandi
2019 Proceedings of the 24th Asia and South Pacific Design Automation Conference on - ASPDAC '19  
If, at one end, we may find even more heterogenous processors composed by a myriad of specialized processing elements, at the other end we may see novel reconfigurable architectures, composed of sets of  ...  Data analytics applications increasingly are complex workflows composed of phases with very different program behaviors (e.g., graph algorithms and machine learning, algorithms operating on sparse and  ...  The appearance of new synthesis tools, based on parallel programming interfaces, also has reinforced interest regarding FPGAs in HPC environments.  ... 
doi:10.1145/3287624.3288754 dblp:conf/aspdac/CastellanaMTLFF19 fatcat:ip4n6z5ghzdubmzs7g6vsq3jmu

Parallelism reduction method in the high-level VLSI synthesis implementation

Darya Sergeevna Romanova, Oleg Vladimirovich Nepomnyashchiy, Igor Nikolayevich Ryzhenko, Alexander Ivanovich Legalov, Natalya Yurievna Sirotinina
2022 Proceedings of the Institute for System Programming of RAS  
The method and language of parallel programming for functional flow synthesis of design solutions is presented.  ...  The main feature of the developed method is the introduction of the additional meta-layer into the synthesis process. Algorithms for the parallelism reduction have been developed.  ...  The article is based on the materials of the report at the Seventh International Conference «Actual Problems of System and Software Engineering» (APSSE 2021).  ... 
doi:10.15514/ispras-2022-34(1)-5 fatcat:yygd65qoc5gy7ewainufjev6hu

Page 4800 of Mathematical Reviews Vol. , Issue 86j [page]

1986 Mathematical Reviews  
They contain a survey of various parallel computer architectures, describe the architecture of data- flow computers, discuss the interrelationship of algorithms and software with the architecture of a  ...  Chapter 6 is devoted to a project on the programming technology of parallel architectures. A special mathematical logic, the so- called structure logic (SL), is developed.  ... 

Hierarchical Dataflow Model for efficient programming of clustered manycore processors

Julien Hascoet, Karol Desnos, Jean-Francois Nezan, Benoit Dupont de Dinechin
2017 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP)  
Programming Multiprocessor Systems-on-Chips (MPSoCs) with hundreds of heterogeneous Processing Elements (PEs), complex memory architectures, and Networks-on-Chips (NoCs) remains a challenge for embedded  ...  Dataflow Models of Computation (MoCs) are increasingly used for developing parallel applications as their high-level of abstraction eases the automation of mapping, task scheduling and memory allocation  ...  Although many programming APIs adopting 978-1-5090-4825-0/17/$31.00 c 2017 IEEE various MoCs can be found in literature, no universal parallel programming model fitting all architectures and all applications  ... 
doi:10.1109/asap.2017.7995270 dblp:conf/asap/HascoetDND17 fatcat:zrl6ffctonhrzixhzhh35nbzdy

Guest Editorial: Special Section on On-Chip Networks

L.-S. Peh, T.M. Pinkston
2005 IEEE Transactions on Parallel and Distributed Systems  
Bhattacharyya focuses on a specific phase of the synthesis design flow of on-chip networks for application-specific SoCs: the topology mapping phase.  ...  A S technology scaling enables the integration of billions of transistors on a chip, economies of scale is prompting the move toward parallel chip architectures with both application-specific systems-on-a-chip  ... 
doi:10.1109/tpds.2005.19 fatcat:yo5h46cqhnacxa2azr6wuicaja

Embedded computer architecture and automation

B. Ramakrishna Rau, M.S. Schlansker
2001 Computer  
The distinct requirements of embedded computing, coupled with emerging technologies, will stimulate system and processor specialization, customization, and computer architecture automation.  ...  Acknowledgments Our present and past colleagues in the Compiler and Architecture Research group at Hewlett-Packard Laboratories who worked with us in developing the PICO system have greatly influenced  ...  the ideas and opinions expressed in this article: Rob Schreiber, Shail Aditya, Vinod Kathail, Scott Mahlke, Darren Cronquist, Mukund Sivaraman, Santosh Abraham, Greg Snider, Sadun Anik, and Richard Johnson  ... 
doi:10.1109/2.917544 fatcat:e5pszcfco5fjziqjifbuu7vnwa

ASAM: Automatic Architecture Synthesis and Application Mapping

Lech Jozwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri (+1 others)
2012 2012 15th Euromicro Conference on Digital System Design  
.  Abstract -This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable applicationspecific instruction-set  ...  It presents an overview of the research being currently performed in the scope of the European project ASAM (Architecture Synthesis and Application Mapping) of the ARTEMIS program.  ...  ) of the ARTEMIS program.  ... 
doi:10.1109/dsd.2012.28 dblp:conf/dsd/JozwiakLCMMMDGJPPTR12 fatcat:et5s2vcnhzbfrae2jufsqzq4gy

Evaluating OpenCL as a Standard Hardware Abstraction for a Model-based Synthesis Framework: A Case Study

Omair Rafique, Klaus Schneider
2019 Proceedings of the 7th International Conference on Model-Driven Engineering and Software Development  
Altogether, we envision an automatic synthesis that maps models using a combination of different MoCs on heterogeneous hardware architectures.  ...  To automatically bridge this gap, we envisage a holistic model-based design framework for heterogeneous synthesis that allows the modeling of a system using a combination of different MoCs.  ...  for better exploiting the parallelism offered by heterogeneous architectures.  ... 
doi:10.5220/0007470503880395 dblp:conf/modelsward/Rafique019 fatcat:fdf4usk4ing67eky2ft7s7zcmq

DEFACTO: A design environment for adaptive computing technology [chapter]

Kiran Bondalapati, Pedro Diniz, Phillip Duncan, John Granacki, Mary Hall, Rajeev Jain, Heidi Ziegler
1999 Lecture Notes in Computer Science  
DEFACTO leverages parallelizing compiler technology based on the Stanford SUIF compiler.  ...  In this paper we describe DEFACTO, an end-to-end design environment aimed at bridging the gap in tools for adaptive computing by bringing together parallelizing compiler technology and synthesis techniques  ...  For this particular example the code generation phase can explore parallelism or pipelining in the execution of the various iteration of the task G1 loop body.  ... 
doi:10.1007/bfb0097941 fatcat:elpp746jnnfr5ellraoxcsod4i

Prototyping Embedded Dsp Systems - From Specification To Implementation

Zoran Salcic
2004 Zenodo  
Publication in the conference proceedings of EUSIPCO, Viena, Austria, 2004  ...  For example, FPGAs and ASICs enable implementation of parallel architectures. If we target an instruction set architecture (ISA), then the problem is how to map the algorithm on the architecture.  ...  for analysis of system behaviour are programs running on the usual PC platform.  ... 
doi:10.5281/zenodo.38706 fatcat:navkxtet35ae7hpjep3xrbe6oi

Verification and Simulation of New Designed NAND Flash Memory Controller

K. Agarwal, V. K. Magraiya, A. K. Saxena
2013 2013 International Conference on Communication Systems and Network Technologies  
As the cell size of NAND flash memory is reduced every year the performance, reliability, speed is increased very rapidly. NAND flash memory is programmed on page by page basis.  ...  For the better use of NAND type flash memory we design a new Arithmetical and Logical Unit (ALU) for calculating addition, subtraction, increment, decrement operations etc.  ...  As shows in Figure-6 the RTL view of ALU was generated after the synthesis and it is display the internal architecture of ALU.  ... 
doi:10.1109/csnt.2013.163 fatcat:zj5bspkloretzmmaobgy2bpuli

Design, Synthesis, and Test of Networks on Chips

P.P. Pande, C. Grecu, A. Ivanov, R. Saleh, G. De Micheli
2005 IEEE Design & Test of Computers  
(See the "Programming models for NoCs" sidebar on p. 406.)  ...  A programming model for parallel systems like NoCs is a description of the basic components, their properties and available operations, and their synchronization. 1 The two primary parallel computing  ... 
doi:10.1109/mdt.2005.108 fatcat:ftg32fzp2jelppgskbqb34ehiy
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