Filters








351 Hits in 3.5 sec

On the Simulation of Time-Triggered Systems on a Chip with BIP [article]

Jan Olaf Blech, Benoit Boyer, Thanh Hung Nguyen
2011 arXiv   pre-print
In this report, we present functional models for software and hardware components of Time-Triggered Systems on a Chip (TTSoC). These are modeled in the asynchronous component based language BIP.  ...  Our approach allows us to simulate and validate aspects of the software system at an early stage in the development process and without the need to have the TTSoC hardware at hand.  ...  Acknowledgments This work has been supported by the European research project ACROSS under the Grant Agreement ARTEMIS-2009-1-100208.  ... 
arXiv:1109.5505v1 fatcat:3c7mxz5oajdlndtz4p2rbv63le

Tribeca

Meeta S. Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David Brooks
2009 Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture - Micro-42  
We further illustrate the spatial and temporal characteristics of parameter variations by combining best-known modeling frameworks for P, V, and T with a POWER6-like microprocessor performance simulator  ...  Irregularities during the fabrication of a microprocessor and variations of voltage and temperature during its operation widen worst-case timing margins of the design-degrading performance significantly  ...  The simulated workloads are a subset of the SPEC CPU2006 benchmark suite along with one TPC-C benchmark.  ... 
doi:10.1145/1669112.1669168 dblp:conf/micro/GuptaRBWB09 fatcat:iqgwublgtfh4lec6onqzd35jk4

Enhancing the Tolerance to Power-Supply Instability in Digital Circuits

J. Semiao, J. Freijedo, J.J. Rodriguez Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)  
Experimental results based on SPICE simulations for simple combinational, pipeline and finite-state machine (FSM) circuits are used to demonstrate the usefulness of the proposed methodology.  ...  Two architectures are presented, and one of them is shown to be effective. The key module is a Clock Stretching Logic (CSL) block, used to increase CDC according to V DD -V SS variations.  ...  INTRODUCTION ignal integrity is becoming a significant problem for high-performance IC products, namely highspeed gigahertz nanometer System-on-Chip (SoC) [1] .  ... 
doi:10.1109/isvlsi.2007.44 dblp:conf/isvlsi/SemiaoFRVSTT07 fatcat:slhlggdxwrfhlfwvyzx6bsxtme

Rigorous System Design

Joseph Sifakis
2012 Foundations and Trends® in Electronic Design Automation  
Separation of concerns: Keep separate what functionality is provided (application SW) from how its is implemented by using resources of the target platform Coherency: Based on a single model to avoid gaps  ...  between steps due to the use of semantically unrelated formalisms e.g. for programming, HW description, validation and simulation, breaking continuity of the design flow and jeopardizing its coherency  ...  of primitives  Expressiveness: achievement of a given coordination with a minimum of mechanism and a maximum of clarity q 1 -a q' 1 q 1 q 2 -a  q' 1 q 2 q 1 -a q' 1 q 2 -c q' 2 q 1 q 2 -ac  q'  ... 
doi:10.1561/1000000034 fatcat:gwvs34l3njesnete23mjsq7oce

Low-Overhead Core Swapping for Thermal Management [chapter]

Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita Shayesteh, Tim Sherwood
2005 Lecture Notes in Computer Science  
We further investigate activity migration (core swapping) as a means of controlling the thermal profile of the chip in this study.  ...  To combat these trends, we evaluate the thermal efficiency of the microcore architecture, a deeply decoupled processor core with larger structures factored out as helper engines.  ...  Methodology The simulator used in this study was derived from the SimpleScalar/Alpha 3.0 tool set [6] , a suite of functional and timing simulation tools for the Alpha AXP ISA.  ... 
doi:10.1007/11574859_4 fatcat:q2ppghtpkvgy5dlnpm6xlimafa

DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems

Georgia Giannopoulou, Peter Poplavko, Dario Socci, Pengcheng Huang, Nikolay Stoimenov, Paraskevas Bourgos, Lothar Thiele, Marius Bozga, Saddek Bensalem, Sylvain Girbal, Madeleine Faugere, Romain Soulat (+1 others)
2018 Design automation for embedded systems  
implementation, using the principle 'what you verify is what you generate' which is based on a novel variant of task automata (BIP).  ...  We demonstrate the applicability of our design flow with an industrial avionic test case on the state-of-the-art Kalray MPPA R -256.  ...  on a network-on-chip [62] .  ... 
doi:10.1007/s10617-018-9206-3 fatcat:byr66bwtdrca5b5ugryv7anpte

S3CBench: Synthesizable Security SystemC Benchmarks for High-Level Synthesis

Nandeesha Veeranna, Benjamin Carrion Schafer
2017 Journal of Hardware and Systems Security  
A repository of RT-level benchmarks with different types of Hardware Trojan is available at the Trust-hub (https://www.trust-hub.org/resources/ benchmarks).  ...  This work presents an open-source benchmark suite of synthesizable behavioral descriptions with different types of hardware Trojan.  ...  On the other hand, the International Technology Roadmap for Semiconductors (ITRS) suggests that by 2020 a 10× productivity increase for designing complex System on Chips (SoCs) is needed.  ... 
doi:10.1007/s41635-017-0014-1 dblp:journals/jhss/VeerannaS17a fatcat:gow7ng34cfbqldmxyub574scnq

Mixed-Critical Systems Design with Coarse-Grained Multi-core Interference [chapter]

Peter Poplavko, Rany Kahil, Dario Socci, Saddek Bensalem, Marius Bozga
2016 Lecture Notes in Computer Science  
We compile the application into a representation in this language and combine the result with a resource manager into a joint software design used to deploy the given system on the target platform.  ...  of system functions priority over low-critical ones in emergency situations.  ...  The executable is linked with BIP RTE (the 'engine') and executes on a platform on top of the real-time operating system.  ... 
doi:10.1007/978-3-319-47166-2_42 fatcat:pzkiklqvtrcrbcasnbfslmcavm

Execution of heterogeneous models for thermal analysis with a multi-view approach

Amani Khecharem, Carlos Gomez, Julien Deantoni, Frederic Mallet, Robert De Simone
2014 Proceedings of the 2014 Forum on Specification and Design Languages (FDL)  
The framework is illustrated on a CPU thermal manager case study with a joint simulation of both its functional and non-functional models.  ...  To deal with the high complexity of embedded systems, engineers rely on high-level heterogeneous models that combine functional and non-functional aspects, hardware/software artifacts, structural and behavioral  ...  In this case, the functional simulation sets the chip activity according to the chip temperature, but the chip temperature in tools like Aceplorer or Hotspot requires the chip activity.  ... 
doi:10.1109/fdl.2014.7119366 dblp:conf/fdl/KhecharemGDMS14 fatcat:jg65rjqmf5elncx425bqd6qifq

Overview of the LLUMC/UCSC/CSUSB Phase 2 Proton CT Project

R W Schulte, V Bashkirov, R Johnson, H F-W Sadrozinski, K E Schubert
2012 Transactions of the American Nuclear Society  
The content of this paper is solely the responsibility of the authors and does not necessarily represent the official views of the National Institute of Biomedical Imaging And Bioengineering or the National  ...  Acknowledgments The project described is supported by Award Number R01EB013118 from the National Institute of Biomedical Imaging and Bioengineering (NIBIB).  ...  Both SAP and BIP allow the system matrix of the linear system to be partitioned into blocks or strings of rows.  ... 
pmid:24771878 pmcid:PMC3999917 fatcat:6cm24fy5vjcyncr42usdwqarta

NON-SEQUENTIAL INSTRUCTION CACHE PREFETCHING FOR MULTIPLE–ISSUE PROCESSORS

ALEXANDER V. VEIDENBAUM, QINGBO ZHAO, ABDUHL SHAMEER
1999 International journal of high speed computing  
This may not always be possible or desirable for an on-chip I-cache because the cycle time of the cache is determined by its size [JoWi94] and is a major factor in determining the CPU clock speed.  ...  For example, the DEC Alpha-21164 has a unified on-chip second-level cache (96KB) and an off-chip third-level cache (typically 2MB).  ...  For the second class, a branch has to trigger prefetching along one of the two possible paths as specified by a branch predictor.  ... 
doi:10.1142/s0129053399000065 fatcat:epd6pr67orbahlcrysjl5snz2q

Runtime verification of component-based systems in the BIP framework with formally-proved sound and complete instrumentation

Yliès Falcone, Mohamad Jaber, Thanh-Hung Nguyen, Marius Bozga, Saddek Bensalem
2013 Journal of Software and Systems Modeling  
BIP is a powerful and expressive component-based framework for the formal construction of heterogeneous systems. Our method augments BIP systems with monitors to check specifications at runtime.  ...  That is, adding a monitor in the system should not deteriorate executions of the initial system time and memory wise. Motivations for using monitoring to validate component-based systems.  ...  The authors would like to warmly thank the anonymous reviewers for their insightful  ... 
doi:10.1007/s10270-013-0323-y fatcat:2e27dekw3rcbbayrhmms2baeqq

Model-based Design and Formal Analysis of Arbitration Protocols on Multiple-Bus Architecture

Imene Ben Hafaiedh, Maroua Ben Slimane
2016 International Workshop on Verification and Evaluation of Computer and Communication Systems  
In this paper we propose a high-level formal model of multiple-bus multiprocessor architecture seen as a component-based system.  ...  Moreover, the proposed model of the studied protocols is modeled in a distributed manner which makes the generation of their implementation more interesting and the study of their performance eciency more  ...  The time is computed for a model with 5 processors and 2 buses.  ... 
dblp:conf/vecos/BenhafaiedhS16 fatcat:ondevc2dgzacbkxl4ui6w463zq

Low-Cost and Scalable Platform with Multiplexed Microwell Array Biochip for Rapid Diagnosis of COVID-19

Yang Wang, Kaiju Li, Gaolian Xu, Chuan Chen, Guiqin Song, Zaizai Dong, Long Lin, Yu Wang, Zhiyong Xu, Mingxia Yu, Xinge Yu, Binwu Ying (+3 others)
2021 Research  
A polymeric chip with a laser-engraved microwell array was developed to process the reaction between the primers and the respiratory swab RNA extracts, based on reverse transcriptase loop-mediated isothermal  ...  To achieve clinically acceptable performance, we synthesized a group of six primers to identify the conserved regions of the ORF1ab gene of SARS-CoV-2.  ...  Acknowledgments The authors thank Luo Feng from Wuhan Chain Medical Labs; Wei Fan from Zhongnan Hospital of Wuhan University; Xinqiong Li and Weidan Yuan from West China Hospital, Sichuan University and  ... 
doi:10.34133/2021/2813643 pmid:33796859 pmcid:PMC7982056 fatcat:c4z2ykaqrja5hn47jbbfaratoq

Adaptive Set-Granular Cooperative Caching

Dyer Rolan, Basilio B. Fraguela, Ramon Doallo
2012 IEEE International Symposium on High-Performance Comp Architecture  
This provides lower latency and isolation, at the cost of depriving the system of the possibility of reassigning underutilized resources.  ...  A way of taking advantage of underutilized resources in other private LLCs in the same chip is to use the coherence mechanism to determine the state of those caches and spill lines to them.  ...  The authors are also members of the european HiPEAC network of excellence.  ... 
doi:10.1109/hpca.2012.6169028 dblp:conf/hpca/RolanFD12 fatcat:vaqg7cjhtnfsna23nhpr4ivuqa
« Previous Showing results 1 — 15 out of 351 results