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Defeating Hardware Prefetchers in Flush+Reload Side-channel Attack
2021
IEEE Access
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An important class of these attacks is based on measurements from cache memory systems. ...
.,-* (2) Since hardware prefetching does not generate additional false negatives, the mathematical expectation of false positives is the only indicator to evaluate the impact of hardware prefetching on ...
doi:10.1109/access.2021.3056190
fatcat:yce6gxgjtnhmbg6i4fxizg2iui
DNS Tunneling Detection by Cache-Property-Aware Features
2021
IEEE Transactions on Network and Service Management
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In this study, we propose a DNS tunneling detection method based on the cacheproperty-aware features. ...
In the context of data exfiltration by DNS tunneling, the malware connects directly to the DNS cache server and the generated DNS tunneling queries produce cache misses with absolute certainty. ...
ACKNOWLEDGMENT The authors thank the anonymous reviewers for their constructive comments. ...
doi:10.1109/tnsm.2021.3078428
fatcat:f4wa5uro5vbdnkqv6yn2mc5fqy
Information Batteries: Storing Opportunity Power with Speculative Execution
[article]
2021
arXiv
pre-print
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We also evaluate the space of operation for an IB system, to identify the best case efficiency of any IB system for a given power and compute regime. ...
In particular, we implement one specific IB prototype by augmenting the Rust compiler to enable transparent function-level precomputation and caching. ...
Negative power prices are the best indicator of uneconomic production. ...
arXiv:2108.01035v1
fatcat:ko7ketzhxjgphn4iszcp3bzhqa
Lifetime Reliability Aware Architectural Adaptation
2013
2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems
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Relentless CMOS technology scaling has resulted in increased on-chip temperature leading to serious concerns about lifetime reliability of micro-processors. ...
We employ an online Bayesian classifier that can efficiently detect the reliable configurations, while a performance prediction model selects the one with best performance among all the reliable configurations ...
ACKNOWLEDGMENT This work was supported by Singapore Ministry of Education Academic Research Fund Tier 2, MOE2009-T2-1-033. ...
doi:10.1109/vlsid.2013.192
dblp:conf/vlsid/MuthukaruppanM13
fatcat:fj4c26s27fenjmnqtdtet37l4i
A Gain-Tuning Dynamic Negative Sampler for Recommendation
2022
Proceedings of the ACM Web Conference 2022
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The existing methods usually exploit various negative samplers (i.e., heuristic-based or GAN-based sampling) on user feedback data to improve the quality of negative samples. ...
Selecting reliable negative training instances is the challenging task in the implicit feedback-based recommendation, which is optimized by pairwise learning on user feedback data. ...
Gain-aware Negative Sampler Given the risk of introducing false negative instances, the quality of negative samples needs to be measured in a more reliable way. ...
doi:10.1145/3485447.3511956
fatcat:s7bfybdb4fepffmzsbg55cvw5m
Cache index-aware memory allocation
2011
Proceedings of the international symposium on Memory management - ISMM '11
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Poor placement of data blocks in memory may negatively impact application performance because of an increase in the cache conflict miss rate [18] . ...
the placement of blocks so that allocations for different threads and processes start on different cache indexes. ...
That is, the cache page size is less than the system base page size of 8KB.
B. ...
doi:10.1145/1993478.1993486
dblp:conf/iwmm/AfekDM11
fatcat:axhbmkpjm5atfmptz5n24c2z2e
Cache index-aware memory allocation
2011
SIGPLAN notices
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Poor placement of data blocks in memory may negatively impact application performance because of an increase in the cache conflict miss rate [18] . ...
the placement of blocks so that allocations for different threads and processes start on different cache indexes. ...
That is, the cache page size is less than the system base page size of 8KB.
B. ...
doi:10.1145/2076022.1993486
fatcat:xf7z3b7bcnf45d3unnhl2zu5sy
An Effective Context Sensitive Offloading System for Mobile Cloud Environments using Support Value-based Classification
2019
Scalable Computing : Practice and Experience
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This paper presents an MCC offloading system based on internet offloading choices. This system guarantees the conservation of battery life and reduced execution time. ...
The result indicates the presented offloading framework can choose reasonable cloud assets depending on various contexts of the mobile devices and achieve significant performance enhancement. ...
False negative rate (FNR) is the number of positives which gives negative results. FNR is computed using Equation 4.5.
. Precision. ...
doi:10.12694/scpe.v20i4.1570
fatcat:mehlwzycxnealg7audestwpuby
PDR: A Prevention, Detection and Response Mechanism for Anomalies in Energy Control Systems
[chapter]
2013
Lecture Notes in Computer Science
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PDR is based on a conglomeration of technologies and on a set of essential components with the purpose of offering situational awareness irrespective of where the system is located. ...
With this, the entire system is able to know the real reliability of its services and its activity in remote substations at all times. ...
In our case, this base station is a powerful gateway device. ...
doi:10.1007/978-3-642-41485-5_3
fatcat:kuarr3dgz5dujkzqubm6baqc4y
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
2009
SIGARCH Computer Architecture News
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If one can accurately predict critical threads in a parallel program, then one can respond in a variety of ways. ...
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. ...
The false negatives rate (dark bar) indicates how often a steal is unsuccessful because its chosen target has no work, despite the presence of a stealable task elsewhere in the system. ...
doi:10.1145/1555815.1555792
fatcat:barphpqrnnegdhtpl3l2q3smly
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
2009
Proceedings of the 36th annual international symposium on Computer architecture - ISCA '09
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If one can accurately predict critical threads in a parallel program, then one can respond in a variety of ways. ...
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. ...
The false negatives rate (dark bar) indicates how often a steal is unsuccessful because its chosen target has no work, despite the presence of a stealable task elsewhere in the system. ...
doi:10.1145/1555754.1555792
dblp:conf/isca/BhattacharjeeM09
fatcat:5mkw5it7mne5lnxwszq2t3tmuq
The evicted-address filter
2012
Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12
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We compare our EAF-based mechanism to ve state-of-the-art mechanisms that address cache pollution or thrashing, and show that it provides signi cant performance improvements for a wide variety of workloads ...
In a system with limited cache space, we would ideally like to prevent 1) cache pollution, i.e., blocks with low reuse evicting blocks with high reuse from the cache, and 2) cache thrashing, i.e., blocks ...
We acknowledge the generous support of AMD, Intel, Oracle, and Samsung. ...
doi:10.1145/2370816.2370868
dblp:conf/IEEEpact/SeshadriMKM12
fatcat:byttqcggj5hotmdg5vyujcpjli
Using hardware transactional memory for data race detection
2009
2009 IEEE International Symposium on Parallel & Distributed Processing
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We propose the concept of lightweight debug transactions that exploit the conflict detection mechanisms of transactional memory systems to perform data race detection. ...
We present a proof-of-concept simulation prototype, and evaluate it on data races injected into applications from the SPLASH-2 suite. ...
The eviction of a cache line with either of its DR/DW bits set could result in false negatives, i.e., missing a dynamic data race instance. ...
doi:10.1109/ipdps.2009.5161006
dblp:conf/ipps/GuptaSCIR09
fatcat:erm6mlqi4vhlbh3r4qil4x3mjy
SMT-Aware Instantaneous Footprint Optimization
2016
Proceedings of the 25th ACM International Symposium on High-Performance Parallel and Distributed Computing - HPDC '16
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Finally, we develop a lightweight performance tool, named SMTAnalyzer, to effectively identify the optimization opportunities in the source code of multithreaded programs. ...
Experiments on three SMT architectures (i.e., Intel Xeon, IBM POWER7, and Intel Xeon Phi) demonstrate that our proposed SMT-aware optimization scheme can significantly improve the performance for general ...
The Pacific Northwest National Laboratory is operated by Battelle for the U.S. Department of Energy under contract DE-AC05-76RL01830. ...
doi:10.1145/2907294.2907308
dblp:conf/hpdc/RoyLS16
fatcat:gmj7i7s2obc2flsjzjgytihmxq
Stash directory: A scalable directory for many-core coherence
2014
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
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However, their limited associativity disallows the one-to-one correspondence of directory entries to cached blocks, rendering them inadequate in tracking all cached blocks. ...
Unless the directory storage is generously overprovisioned, conflicts will force frequent invalidations of cached blocks, severely jeopardizing the system performance. ...
The results, which are based on a 1/4× under-provisioned directory size and LRU replacement policy, indicate that many directory evictions will invalidate private cached blocks (72%), while 80% of them ...
doi:10.1109/hpca.2014.6835928
dblp:conf/hpca/DemetriadesC14
fatcat:6f35kve4k5gxdodqhvcebz5k4y
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