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On the Design of Reliable Boolean Circuits That Contain Partially Unreliable Gates

Dan Kleitman, Tom Leighton, Yuan Ma
1997 Journal of computer and system sciences (Print)  
We investigate a model of gate failure for Boolean circuits in which a faulty gate is restricted to output one of its input values.  ...  Our model has the advantage that it allows us to design Boolean circuits that can tolerate worst-case faults, as well as circuits that have arbitrarily high success probability in the case of random faults  ...  Special thanks t o Ehrenborg for many stimulating discussions in the early stage of this research and for suggesting the story of Charles in the Gate Store.  ... 
doi:10.1006/jcss.1997.1531 fatcat:5xek2td6nbh75lj4zimmhrjcry

On the design of reliable Boolean circuits that contain partially unreliable gates

D. Kleitman, T. Leighton, Y. Ma
Proceedings 35th Annual Symposium on Foundations of Computer Science  
We investigate a model of gate failure for Boolean circuits in which a faulty gate is restricted to output one of its input values.  ...  Our model has the advantage that it allows us to design Boolean circuits that can tolerate worst-case faults, as well as circuits that have arbitrarily high success probability in the case of random faults  ...  Special thanks t o Ehrenborg for many stimulating discussions in the early stage of this research and for suggesting the story of Charles in the Gate Store.  ... 
doi:10.1109/sfcs.1994.365682 dblp:conf/focs/KleitmanLM94 fatcat:v5fqjqne3ncq7j43ybbtij4vqy

Page 5147 of Mathematical Reviews Vol. , Issue 99g [page]

1999 Mathematical Reviews  
Tom [Leighton, Frank Thomson} (1-MIT; Cambridge, MA); Ma, Yuan (1-MIT-C; Cambridge, MA) On the design of reliable Boolean circuits that contain partially unreliable gates.  ...  Our model has the advantage that it allows us to design Boolean circuits that can tolerate worst-case faults, as well as circuits that have arbitrarily high success probability in the case of random faults  ... 

Hard-decision decoding of LDPC codes under timing errors: Overview and new results

Srdan Brkic, Predrag Ivanis, Bane Vasic
2017 2017 25th Telecommunication Forum (TELFOR)  
This paper contains a survey on iterative decoders of low-density parity-check (LDPC) codes built form unreliable logic gates.  ...  Furthermore, we show that concept of guaranteed error correction can be applied to the decoders made partially from unreliable components.  ...  Indeed, we prove that decoders partially built from unreliable gates can achieve zero error probability. III.  ... 
doi:10.1109/telfor.2017.8249332 fatcat:jgoic6pfpnezbdy2pi4hjhzxoy

A defect- and fault-tolerant architecture for nanocomputers

Jie Han, Pieter Jonker
2003 Nanotechnology  
The system performance of this architecture is evaluated by studying its reliability, i.e. the probability of system survival.  ...  Our evaluation shows that the suggested architecture can tolerate a device error rate of up to 10 −2 , with multiple redundant components; the structure is efficiently robust against both permanent and  ...  This work is supported by Delft University of Technology in its DIRC project 'Novel computation structures based on quantum devices'.  ... 
doi:10.1088/0957-4484/14/2/324 fatcat:t7whyj6l5rboxkw37dx22m4gby

Analysis of the Signal Reliability Measure and an Evaluation Procedure

Koren
1979 IEEE transactions on computers  
measure of digital circuits, known as functional reliability, assumes that the circuit fails whenever a fault is present in it.  ...  A different reliability measure, known as signal reliability, is the probability that the circuit output is correct.  ...  The first measure is calledfunctional reliability and is the probability that the circuit realizes the desired design function.  ... 
doi:10.1109/tc.1979.1675326 fatcat:cpdls2nzwve5vi7fmyeu5q54mi

The Search for Alternative Computational Paradigms

Naresh R. Shanbhag, Subhasish Mitra, Gustavode de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet Roychowdhury, Douglas Jones, Jan M. Rabaey
2008 IEEE Design & Test of Computers  
&EXTREMES OF PROCESS variation, noise, soft errors, and other nonidealities in nanometer process technologies threaten to nullify the intrinsic advantages of scaling that the semiconductor industry has  ...  An ideal CNFET technology enables the design of digital circuits with a 133 energy-delay product (EDP) advantage and a 53 speed advantage over 32-nm silicon CMOS. 2 However, these and other post-silicon  ...  Acknowledgments We acknowledge the support of the Gigascale Systems Research Center (GSRC).  ... 
doi:10.1109/mdt.2008.113 fatcat:7le3xj4w6rcjnako5ulahgxfhm

Algebra of switching networks

Andrey Mokhov
2015 IET Computers & Digital Techniques  
Relays were very unreliable due to mechanical switching, therefore the issue of network reliability was very important at that time.  ...  It also brings in new methods of circuit composition that are of high importance for modern system design and development, which heavily rely on the reuse of components and interfaces.  ...  Special thanks go to the participants of the Designing with Uncertainty -Opportunities & Challenges 2014 workshop for their valuable comments on the earlier version of this work.  ... 
doi:10.1049/iet-cdt.2014.0135 fatcat:xnbjeyzhbzf3nhyzbcdvknzvaq

Design Constraints for Nanometer Scale Quantum Computers [article]

Ronnie Mainieri
1994 arXiv   pre-print
I have analyzed current device capabilities and explored two general design requirements for the design of computers: error correction and long range connections.  ...  I consider the roles of electromigration through thin wires, circuit layout, and error rates for devices with small gain.  ...  I would also like to thank Mark Reed for allowing me to adapt one of his slides for this publication ( gure 5). This work was supported by the Department of Energy.  ... 
arXiv:cond-mat/9410109v1 fatcat:c664xtbc65dixcieryjqiscwp4

Robust privacy-preserving fingerprint authentication

Ye Zhang, Farinaz Koushanfar
2016 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)  
We show evaluations of our modified matching algorithm on a standard fingerprint database to demonstrate its reliability.  ...  The implementation of privacy-preserving fingerprint authentication using Synopsis Design Compiler shows the efficiency and scalability of the proposed methodologies.  ...  The main reason is that the circuit size (or total number of gates) of combinational logic is proportional to the number of inputs.  ... 
doi:10.1109/hst.2016.7495547 dblp:conf/host/ZhangK16 fatcat:zs4kstdv3ng2zldog2bsuzkn3e

Kernel Ada to unify hardware and software design

Sy Wong, Gertrude Levine
1998 Proceedings of the 1998 annual ACM SIGAda international conference on Ada - SIGAda '98  
Most important, the need for reliable constructs is crucial for the design of integrated circuits. What is retained in Kernel Ada is based solely on necessity.  ...  Reliability should also be a goal for beginning students; indeed, the constructs that are excluded from Kernel Ada are exactly those that are the most unreliable for teaching purposes.  ... 
doi:10.1145/289524.289529 dblp:conf/sigada/WongL98 fatcat:totua4unfze2le7jd7qf6fl33a

Kernel Ada to unify hardware and software design

Sy Wong, Gertrude Levine
1998 ACM SIGAda Ada Letters  
Most important, the need for reliable constructs is crucial for the design of integrated circuits. What is retained in Kernel Ada is based solely on necessity.  ...  Reliability should also be a goal for beginning students; indeed, the constructs that are excluded from Kernel Ada are exactly those that are the most unreliable for teaching purposes.  ... 
doi:10.1145/301687.289529 fatcat:ucz24b772ff6rkf7yuyikwtcfe

A Fault Tolerant Voter Circuit for Triple Modular Redundant System

Mohammed Hadifur Rahman
2017 Journal Electrical and Electronic Engineering  
A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components.  ...  Robustness of the voter circuit defines the reliability of the fault tolerant system. This paper provides simulation results and analysis of a fault tolerant voter circuit.  ...  But the increment in reliability depends on an assumption that the voter block is free from the same failures that the rest of the design is facing.  ... 
doi:10.11648/j.jeee.20170505.11 fatcat:nxkryckqhjhivobrikkw7ivppq

Aspects of systems and circuits for nanoelectronics

K.F. Goser, C. Pacha, A. Kanstein, M.L. Rossmann
1997 Proceedings of the IEEE  
This paper analyzes the effect of this technological progress on the design of nanoelectronic circuits and describes computational paradigms revealing novel features such as distributed storage, fault  ...  A tremendous number of devices, a limitation of wiring, and very low power dissipation density are design constraints of future nanoelectronic circuits composed of quantum-effect devices.  ...  Nevertheless, there is no doubt that LTG's will only become an alternative to traditional Boolean logic, if the costs of a single threshold gate are comparable to those of Boolean gates.  ... 
doi:10.1109/5.573741 fatcat:ck6njzh3fja27atr7vuqmsc6oe

Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design

Marti Anglada, Ramon Canal, Juan Luis Aragon, Antonio Gonzalez
2018 IEEE Transactions on Sustainable Computing  
This paper presents a methodology to estimate in early stages of the design the susceptibility of combinational circuits to particle strikes.  ...  Finally, we analyze the vulnerability of the Decoder, Scheduler, ALU, and FPU of an out-of-order, superscalar processor design.  ...  ACKNOWLEDGMENTS This work has been partially supported by the Spanish Ministry of Economy and Competitiveness and Feder Funds under grant TIN2013-44375-R, by the Generalitat de Catalunya under grant FI-DGR  ... 
doi:10.1109/tsusc.2018.2886640 fatcat:3tdtepbvdrgypel7y3ghglijzy
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