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A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters

Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya
2007 Neurocomputing  
Through circuit simulations and experimental results on a fabricated chip, we demonstrate that our neuromorphic oscillator generates a stable oscillation, and the amplitude and frequency of the oscillation  ...  can be controlled by tuning bias currents over a wide range.  ...  The aim of this work is to implement a neuromorphic oscillator with high controllability of the amplitude and frequency of oscillation.  ... 
doi:10.1016/j.neucom.2006.11.026 fatcat:aipd3xk5hfh5bfgnihxuf4qhw4

Research topic: neuromorphic engineering systems and applications. A snapshot of neuromorphic systems engineering

Tobi Delbruck, André van Schaik, Jennifer Hasler
2014 Frontiers in Neuroscience  
Gupta and Markan (2014) , report on a FG adaptive system for investigating self-organization of image patterns.  ...  Delbruck and Lang (2013) report on the detailed implementation of a fun robotic goalie, which uses a DVS to help track the balls and robot arm. The paper includes measurements of USB latency.  ...  and no conflict of interest exists.  ... 
doi:10.3389/fnins.2014.00424 pmid:25565952 pmcid:PMC4271593 fatcat:f4sgfccrnjgglcna4zn3thgs6e

Criticality as a Set-Point for Adaptive Behavior in Neuromorphic Hardware

Narayan Srinivasa, Nigel D. Stepp, Jose Cruz-Albrecht
2015 Frontiers in Neuroscience  
We believe that this is due to the lack of a clear understanding of how to design self-tuning complex systems.  ...  by such hardware can self-tune local parameters to maintain criticality as a set-point.  ...  Finally, it could also enable the design of truly scalable intelligent systems, since there will not be a need for manual tuning of model or chip parameters by constructing self-tuning critical networks  ... 
doi:10.3389/fnins.2015.00449 pmid:26648839 pmcid:PMC4664726 fatcat:oh7uiyhtzzd53ls5iipmxpwuaq

A location-independent direct link neuromorphic interface

Alexander D. Rast, Johannes Partzsch, Christian Mayr, Johannes Schemmel, Stefan Hartmann, Luis A. Plana, Steve Temple, David R. Lester, Rene Schuffny, Steve Furber
2013 The 2013 International Joint Conference on Neural Networks (IJCNN)  
neural control, such as parameter tuning, for large, complex neural systems, and suggests methods to overcome differences in timescale and simulation model between different platforms.  ...  We propose a UDP-based AER spiking interface that permits direct bidirectional spike communications over standard networks, and demonstrate a practical implementation with two large-scale neuromorphic  ...  The Spinnaker project is supported by the Engineering and Physical Sciences Research Council, partly through the Advanced Processor Technologies Platform Partnership at the University of Manchester, and  ... 
doi:10.1109/ijcnn.2013.6706887 dblp:conf/ijcnn/RastPMSHPTLSF13 fatcat:b2xtlac3wbbx5okaph4erl37ai

Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System [article]

Johannes Partzsch, Christian Mayr, Massimiliano Giulioni, Marko Noack, Stefan Hänzsche, Stefan Scholze, Sebastian Höppner, Paolo Del Giudice, Rene Schüffny
2019 arXiv   pre-print
Real-time coupling of cell cultures to neuromorphic circuits necessitates a neuromorphic network that replicates biological behaviour both on a per-neuron and on a population basis, with a network size  ...  We present a large neuromorphic system composed of 9 chips, with overall 2880 neurons and 144M conductance-based synapses.  ...  As an alternative to the above, we have designed a neuromorphic system based on switched-capacitor (SC) circuits.  ... 
arXiv:1904.10389v1 fatcat:xlqg4anilzfpln7phqo4qhj3ry

Neuromorphic Engineering: From Neural Systems to Brain-Like Engineered Systems

Francesco Carlo Morabito, Andreas G. Andreou, Elisabetta Chicca
2013 Neural Networks  
Torres-Huitzil in the paper ''FPGA implementation of a configurable neuromorphic CPG-based locomotion controller'' investigate on recent developments of neuromorphic hardware systems implemented using  ...  The conclusions of the paper include a summary of ideas and directions for the design of future neuromorphic systems.  ... 
doi:10.1016/j.neunet.2013.07.001 pmid:23899498 fatcat:37jafps74zfj7ftnrodzpiib5y

Neuromorphic Electronic Systems for Reservoir Computing [article]

Fatemeh Hadaeghi
2020 arXiv   pre-print
This chapter provides a comprehensive survey of the researches and motivations for hardware implementation of reservoir computing (RC) on neuromorphic electronic systems.  ...  Due to its computational efficiency and the fact that training amounts to a simple linear regression, both spiking and non-spiking implementations of reservoir computing on neuromorphic hardware have been  ...  I would also like to thank Herbert Jaeger, who provided insight and expertise that greatly assisted this research.  ... 
arXiv:1908.09572v2 fatcat:cimkbnvyrjc3lhixlyufgmqy3i

Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System

Johannes Partzsch, Christian Mayr, Massimiliano Giulioni, Marko Noack, Stefan Hänzsche, Stefan Scholze, Sebastian Höppner, Paolo Del Giudice, Rene Schüffny
2020 Journal of Signal Processing Systems  
Real-time coupling of cell cultures to neuromorphic circuits necessitates a neuromorphic network that replicates biological behaviour both on a per-neuron and on a population basis, with a network size  ...  We present a large neuromorphic system composed of 9 chips, with overall 2880 neurons and 144M conductance-based synapses.  ...  As an alternative to the above, we have designed a neuromorphic system based on switched-capacitor (SC) circuits.  ... 
doi:10.1007/s11265-020-01556-9 fatcat:6q7yk3jljzbenipuhaba37gtxm

Self-Testing Analog Spiking Neuron Circuit

Sarah A. El-Sayed, Luis A. Camunas-Mesa, Bernabe Linares-Barranco, Haralampos-G. Stratigopoulos
2019 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)  
The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology.  ...  In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit.  ...  ACKNOWLEDGMENTS This work has been carried out in the framework of the Penta HADES project. Luis A. Camuñas-Mesa was funded by the VI PPIT through the Universidad de Sevilla.  ... 
doi:10.1109/smacd.2019.8795234 dblp:conf/smacd/El-SayedCLS19 fatcat:txg3ajwwqvevhiage74fpk67l4

SOCC 2019 Author Index

2019 2019 32nd IEEE International System-on-Chip Conference (SOCC)  
Digitally Controllable Passive Variable Slope Gain Equalizer for Wideband Radio Frequency System-on-Chip Applications WP.20 294 A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12  ...  Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard 14.5 GHz Clock Custom Digital Design Methodology Utilizing Back Bias Tuning Capability in 22Nm FD-SOI CMOS Technology A Neural-Network-Based  ... 
doi:10.1109/socc46988.2019.9088078 fatcat:wzmgb42mjzbu5hvgccttlhw3zu

Spintronics for neuromorphic computing [article]

J. Grollier, D. Querlioz, K. Y. Camsari, K. Everschor-Sitte, S. Fukami, M. D. Stiles
2020 arXiv   pre-print
We also explore spintronics-based implementations of neuromorphic computing tasks, such as pattern recognition in an associative memory, and discuss the challenges that exist in scaling up these systems  ...  Here we review the development of spintronic devices for neuromorphic computing.  ...  Data availability The datasets generated and analysed during this study are available from the corresponding authors on reasonable request.  ... 
arXiv:2007.06092v1 fatcat:3m5pfeedmnhq5h7nbjw77zvdi4

Mapping arbitrary mathematical functions and dynamical systems to neuromorphic VLSI circuits for spike-based neural computation

Federico Corradi, Chris Eliasmith, Giacomo Indiveri
2014 2014 IEEE International Symposium on Circuits and Systems (ISCAS)  
This is achieved by means of a network of spiking neurons with multiple weighted connections. The synaptic weights are stored in a 4-bit on-chip programmable SRAM block.  ...  We propose a parallel event-based method for calibrating appropriately the synaptic weights and demonstrate the method by encoding and decoding arbitrary mathematical functions, and by implementing dynamical  ...  In fact, tuning curves relates the spiking response of a neuron to a particular stimulus. We show in Figure 5a tuning curves for all neurons in the neuromorphic chip.  ... 
doi:10.1109/iscas.2014.6865117 dblp:conf/iscas/CorradiEI14 fatcat:imalaetxrrfknaufkvygnf6vcq

A Spike-Based Neuromorphic Architecture of Stereo Vision

Nicoletta Risi, Alessandro Aimar, Elisa Donati, Sergio Solinas, Giacomo Indiveri
2020 Frontiers in Neurorobotics  
We describe a prototype interface designed to enable the emulation of a stereo-vision system on neuromorphic hardware and we quantify the stereo matching performance with two datasets.  ...  Our results provide a path toward the realization of low-latency, end-to-end event-based, neuromorphic architectures for stereo vision.  ...  ACKNOWLEDGMENTS We authors would like to thank Marc Osswald for the fruitful discussions, Chenxi Wu for contributing to the AER interface design, and Dmitrii Zendrikov for helping with the process of calibrating  ... 
doi:10.3389/fnbot.2020.568283 pmid:33304262 pmcid:PMC7693562 fatcat:bwsyksh7kzcwdodjy2qsypu4b4

Photonics for artificial intelligence and neuromorphic computing [article]

Bhavin J. Shastri, Alexander N. Tait, Thomas Ferreira de Lima, Wolfram H. P. Pernice, Harish Bhaskaran, C. David Wright, Paul R. Prucnal
2020 arXiv   pre-print
Neuromorphic photonics offers sub-nanosecond latencies, providing a complementary opportunity to extend the domain of artificial intelligence.  ...  Research in photonic computing has flourished due to the proliferation of optoelectronic components on photonic integration platforms.  ...  In all architectures, there is a need for complex on-chip electronic circuitry for calibration and control of the network parameters, and there is a need to generate light.  ... 
arXiv:2011.00111v2 fatcat:e7s4xr5rwbaknk7mkf7mwkmoci

Compact Device Models for FinFET and Beyond [article]

Darsen D. Lu, Mohan V. Dunga, Ali M. Niknejad, Chenming Hu, Fu-Xiang Liang, Wei-Chen Hung, Jia-Wei Lee, Chun-Hsiang Hsu, Meng-Hsueh Chiang
2020 arXiv   pre-print
We have demonstrated simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU.  ...  In the era of artificial intelligence / deep learning, compact models further enhanced our ability to explore RRAM and other NVM-based neuromorphic circuits.  ...  Acknowledgements The authors would like to express sincere gratitude to Chip Implementation Center (CIC), Hsinchu, Taiwan for providing SPICE simulation environment for RRAM simulations.  ... 
arXiv:2005.02580v1 fatcat:tzr2xfkfnzh65i7l5xguzad43a
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