Filters








11,660 Hits in 3.6 sec

Enhanced Disk-Based Databases Towards Improved Hybrid In-Memory Systems

Samuel Kaspi, Sitalakshmi Venkatraman
2015 Zenodo  
This paper proposes a novel EMA technique and presents a comparative study between disk-based EMA systems and in-memory systems running on hardware configurations of equivalent power in terms of the number  ...  We demonstrate how this prefetching in disk-based systems can yield close to in-memory performance, which paves the way for improved hybrid database systems.  ...  not change the value of the Fig. 7 7 Performance of disk-based EMA (no cost) & in-memory systems (20 Processors, 1 GIPS) Fig. 8 Performance of disk-based EMA (no cost) & in-memory systems (10 Processors  ... 
doi:10.5281/zenodo.1098924 fatcat:nnsuisu2xjcldhen5jmikit5t4

Inherent Limitations of Hybrid Transactional Memory [chapter]

Dan Alistarh, Justin Kopinsky, Petr Kuznetsov, Srivatsan Ravi, Nir Shavit
2015 Lecture Notes in Computer Science  
On the cost of instrumentation and concurrency The following theorems can be proven using the model presented in the previous section.  ...  In this section, we describe the operation of a Hybrid Transactional Memory (HyTM) implementation, in which conventional memory accesses are combined with hardware transactions modelled as cached accesses  ... 
doi:10.1007/978-3-662-48653-5_13 fatcat:mc2wdxbumfh3homcjepsjlpghm

Inherent limitations of hybrid transactional memory

Dan Alistarh, Justin Kopinsky, Petr Kuznetsov, Srivatsan Ravi, Nir Shavit
2017 Distributed computing  
On the cost of instrumentation and concurrency The following theorems can be proven using the model presented in the previous section.  ...  In this section, we describe the operation of a Hybrid Transactional Memory (HyTM) implementation, in which conventional memory accesses are combined with hardware transactions modelled as cached accesses  ... 
doi:10.1007/s00446-017-0305-3 fatcat:odg2m3ikzzg3hazw4svhy2o3aa

Hybrid Transactional Memory Revisited [chapter]

Wenjia Ruan, Michael Spear
2015 Lecture Notes in Computer Science  
The arrival of best-effort hardware transactional memory (TM) creates a challenge for designers of transactional memory runtime libraries.  ...  On the one hand, using hardware TM can dramatically reduce the latency of transactions.  ...  Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.  ... 
doi:10.1007/978-3-662-48653-5_15 fatcat:kjdyxo25sjgnfkfq7omrr332xi

Implementing Atomic Section by Using Hybrid Concurrent Control

Lei Zhao, Yu Zhang
2007 2007 IFIP International Conference on Network and Parallel Computing Workshops (NPC 2007)  
This paper introduces a flexible hybrid concurrent control system which could harmonize the two modes of concurrent control.  ...  Atomic section is an important language feather in multithread synchronizing. So far, it can only be implemented by using pessimistic or optimistic concurrent control singly.  ...  In this section, we describe the details in designing hybrid concurrent control system. Transaction Informally, a transaction is one pass of execution of certain atomic section.  ... 
doi:10.1109/icnpcw.2007.4351558 fatcat:sli4u4goezcl5i2tzu4xg2xp2q

Implementing Atomic Section by Using Hybrid Concurrent Control

Lei Zhao, Yu Zhang
2007 2007 IFIP International Conference on Network and Parallel Computing Workshops (NPC 2007)  
This paper introduces a flexible hybrid concurrent control system which could harmonize the two modes of concurrent control.  ...  Atomic section is an important language feather in multithread synchronizing. So far, it can only be implemented by using pessimistic or optimistic concurrent control singly.  ...  In this section, we describe the details in designing hybrid concurrent control system. Transaction Informally, a transaction is one pass of execution of certain atomic section.  ... 
doi:10.1109/npc.2007.160 fatcat:hjfoxpdrlbcifne34wcywkpxcu

A Multi-version Cache Replacement and Prefetching Policy for Hybrid Data Delivery Environments [chapter]

André Seifert, Marc H. Scholl
2002 VLDB '02: Proceedings of the 28th International Conference on Very Large Databases  
This paper introduces MICP, a novel multiversion integrated cache replacement and prefetching algorithm designed for efficient cache and transaction management in hybrid data delivery networks.  ...  MICP takes into account the dynamically and sporadically changing cost/benefit ratios of cached and/or disseminated object versions by making cache replacement and prefetching decisions sensitive to the  ...  Since multi-versioning imposes additional memory and processor overheads on the clients and the server, we assume that the number of versions maintained in the involved memory levels is restricted.  ... 
doi:10.1016/b978-155860869-6/50080-9 dblp:conf/vldb/SeifertS02 fatcat:pzsub3l3xrejvoxochtommheai

The New Hardware Development Trend and the Challenges in Data Management and Analysis

Wei Pan, Zhanhuai Li, Yansong Zhang, Chuliang Weng
2018 Data Science and Engineering  
In this paper, we first introduce the development trend of the new hardware in computation, storage, and network dimensions.  ...  abundant heterogeneous parallelism, nonvolatile memory with hybrid storage hierarchies, and RDMA-enabled high-speed network.  ...  Acknowledgements The authors would like to thank Mike Dixon for  ... 
doi:10.1007/s41019-018-0072-6 fatcat:kksuldstdvdohpkleq7suyq2ry

Author index

2013 2013 IEEE International Conference on Cluster Computing (CLUSTER)  
in the Cloud On Transactional Memory Concurrency Control in Distributed Real-Time Programs Towards a Unified Object Storage Foundation for Scalable Storage Systems Rountree, Barry Optimizing Power Allocation  ...  Herres-Pawlis, Sonja User-friendly Metaworkflows in Quantum Chemistry Hirve, Sachin On Transactional Memory Concurrency Control in Distributed Real-Time Programs Hoffmann, Alexander User-friendly Metaworkflows  ... 
doi:10.1109/cluster.2013.6702604 fatcat:cxctjrwnfjahhosdn7afzf6dla

Performance Characteristics of Hardware Transactional Memory for Molecular Dynamics Application on BlueGene/Q: Toward Efficient Multithreading Strategies for Large-Scale Scientific Applications

Manaschai Kunaseth, Rajiv K. Kalia, Aiichiro Nakano, Priya Vashishta, David F. Richards, James N. Glosli
2013 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum  
We have investigated the performance characteristics of hardware transactional memory (HTM) on the BlueGene/Q computer in comparison with conventional concurrency control mechanisms, using a molecular  ...  We found that the bookkeeping cost of HTM is high but that the rollback cost is low.  ...  Hardware Transactional Memory on BlueGene/Q TM is an opportunistic concurrency control mechanism.  ... 
doi:10.1109/ipdpsw.2013.29 dblp:conf/ipps/KunasethKNVRG13 fatcat:otsjmjsn7jaaldkvoywxxdge5a

Transactional memory

Håkan Grahn
2010 Journal of Parallel and Distributed Computing  
the state-of-the-art in transactional memory research.  ...  This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances  ...  Hybrid Transactional Memory This section presents some of the most important hybrid transactional memory proposals.  ... 
doi:10.1016/j.jpdc.2010.06.006 fatcat:s3qswzin6jhoneph7taqsnxoxe

Hybrid Transactional Memory with Pessimistic Concurrency Control

Enrique Vallejo, Sutirtha Sanyal, Tim Harris, Fernando Vallejo, Ramón Beivide, Osman Unsal, Adrián Cristal, Mateo Valero
2010 International journal of parallel programming  
Transactional Memory (TM) intends to simplify the design and implementation of the sharedmemory data structures used in parallel software.  ...  One solution is the use of Pessimistic Concurrency Control, but it entails an important performance penalty due to the need of reader-writer locking.  ...  Software reader-writer queuebased locks [27] , as the ones used in our base hybrid TM, reduce contention by using a queue of waiters, at the cost of increased memory usage.  ... 
doi:10.1007/s10766-010-0158-x fatcat:slb7xykb5zghflgazra5bz54tu

Transactional memory and the birthday paradox

Craig Zilles, Ravi Rajwar
2007 Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures - SPAA '07  
This result is particularly important in the context of hybrid TMs, where the small transactions are likely handled in hardware, leaving only the large ones for the STM.  ...  We present an analytical model based on random population of an ownership table by concurrently executing transactions that correctly predicts the trends in measured data.  ...  Finally, we present data on the average maximum size of transactions that a hybrid TM can likely implement in HTM-mode, demonstrating that the hybrid TM's STM should be designed to support transactions  ... 
doi:10.1145/1248377.1248428 dblp:conf/spaa/ZillesR07 fatcat:uurw6earvzbgnektpinpuzeqn4

Reduced Hardware NOrec

Alexander Matveev, Nir Shavit
2015 SIGARCH Computer Architecture News  
Instead of an all-software slow path, in our RH NOrec the slow-path is a "mix" of hardware and software: one short hardware transaction executes a maximal amount of initial reads in the hardware, and the  ...  Our GCC implementation of RH NOrec is promising in that it shows improved performance relative to all prior methods, at the concurrency levels we could test today.  ...  Acknowledgments Support is gratefully acknowledged from the National Science Foundation under grants CCF-1217921, CCF-1301926, and IIS-1447786, the Department of Energy under grant ER26116/DE-SC0008923  ... 
doi:10.1145/2786763.2694393 fatcat:fhmhkclkgfddrplghgef7iea4q

Reduced Hardware NOrec

Alexander Matveev, Nir Shavit
2015 Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '15  
Instead of an all-software slow path, in our RH NOrec the slow-path is a "mix" of hardware and software: one short hardware transaction executes a maximal amount of initial reads in the hardware, and the  ...  Our GCC implementation of RH NOrec is promising in that it shows improved performance relative to all prior methods, at the concurrency levels we could test today.  ...  Acknowledgments Support is gratefully acknowledged from the National Science Foundation under grants CCF-1217921, CCF-1301926, and IIS-1447786, the Department of Energy under grant ER26116/DE-SC0008923  ... 
doi:10.1145/2694344.2694393 dblp:conf/asplos/MatveevS15 fatcat:ezeglqpm35hzzjbzastqf2vzfa
« Previous Showing results 1 — 15 out of 11,660 results