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Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI

E.G. Friedman, S. Powell
1986 IEEE Journal of Solid-State Circuits  
In addition, a model for clock distribution networks which considers the effects of dktributed interconnect impedances on clock skew is described.  ...  In particular, a bierarcbicat design technique for minimizing clock skew within a VLSI circuit and its relative advantages and disadvantages is discussed.  ...  ACKNOWLEDGMENT The authors would like to acknowledge the technical contributions of G. Yacoub, W. Marking, P. Pandya, L. Tsu, D. Barach, T. Cesear, and R. Rapoza. They are also grateful to G.  ... 
doi:10.1109/jssc.1986.1052510 fatcat:xyseq6llfjh5rmucmoliagossa

A Fast Delay Computation for the Hybrid Structured Clock Network

Y. ZOU
2005 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network.  ...  By proper selection of the simulation time step and interval based on Elmore delays, the delay of the clock signal between the clock source and the sink node as well as the clock skews between the sink  ...  The design of the clock networks has huge impacts on the behavior of the synchronized circuits on a chip.  ... 
doi:10.1093/ietfec/e88-a.7.1964 fatcat:rlchsjyurbczdoalvan2ga2qiu

Optimal design-space exploration of streaming applications

Shobana Padmanabhan, Yixin Chen, Roger D. Chamberlain
2011 ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors  
We present a global optimization framework comprising a domain-specific variation of branch-and-bound that reduces search complexity by exploiting the topology of the application's pipelining.  ...  Efficient automatic exploration of this design space is the goal of our research.  ...  DOMAIN-SPECIFIC OPTIMIZATION Branching on a variable decomposes the search space, resulting in subproblems that are less complex.  ... 
doi:10.1109/asap.2011.6043274 dblp:conf/asap/PadmanabhanCC11 fatcat:2obmnjqvevdt5gj7azovousnly

Automated Synthesis of Skew-Based Clock Distribution Networks

José Luis Neves, Eby G. Friedman
1998 VLSI design (Print)  
The methodology is divided into four phases: 1) determination of an optimal clock skew schedule for improving circuit performance and reliability; 2) design of the topology of the clock tree based on the  ...  circuit hierarchy and minimum clock path delays; 3) design of circuit structures to implement the delay values associated with the branches of the clock tree; and 4) design of the geometric layout of  ...  as the complexity of the circuit, the number of transistors, and the design methodology.  ... 
doi:10.1155/1998/72951 fatcat:2bwvufew7rfwjdgtbeffiawnn4

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations

Renshen Wang, Takumi Okamoto, Chung-Kuan Cheng
2009 2009 IEEE International Conference on Computer Design  
be added as (L 1 +L 2 , T) 9 Symmetrical Buffer Insertion With symmetry constraints, the paths can be combined into one The RC-tree network is equivalent to a segmented path from the source to the sinks  ...  Joint optimization of delay and number of buffersCost function = delay (ps) + #buffer * X Minimum #buffer: 21 Conclusions Dynamic programming for symmetrical buffer insertion in zero-skew clock trees The  ...  Future Works Other formulation / optimization objectives  ... 
doi:10.1109/iccd.2009.5413180 dblp:conf/iccd/WangTC09 fatcat:qcigf7ngavbqheod2xibiztgmq

Zero Skew Clock-Tree Optimization With Buffer Insertion/Sizing and Wire Sizing

J.-L. Tsai, T.-H. Chen, C.C.-P. Chen
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Our algorithm can also be used to achieve useful clock skew to facilitate timing convergence and to incrementally adjust the clock tree for design convergence and explore delay-power tradeoffs during design  ...  Clock distribution is crucial for timing and design convergence in high-performance very large scale integration designs.  ...  We assume that the initial routing of the clock tree is given and there exists some buffering and sizing combinations such that the clock tree is zero skew.  ... 
doi:10.1109/tcad.2004.825875 fatcat:7gg3e7ahjvb5dhyyrbitv5qgge

Power Considerations in Network Processor Design [chapter]

Mark A. Franklin, Tilman Wolf
2004 Network Processor Design  
Using a variety of metrics, we explore the design space of network processors and show the performance impact of different system and memory configurations.  ...  Network processors are commonly implemented as systems-on-a-chip with multiple processors, caches, memory interfaces and I/O components on a single chip.  ...  Additionally, the contribution of the branch predictor is ignored since, for simple NP RISC cores, it is not necessary to perform complex branch prediction and, overall, system power is dominated by memory  ... 
doi:10.1016/b978-012198157-0/50005-2 fatcat:vd4okskhunb2dm57zmju6cpnta

Power Optimized Programmable Embedded Controller

Kamaraju M, Lalkishore K, Tilak A.V. N
2010 International Journal of Computer Networks & Communications  
The whole design is captured using VHDL and is implemented on FPGA chip using Xilinx .The architecture and clock gating technique together is found to reduce the power consumption by 33.33% of total power  ...  The CPU designed supports i) smart instruction set, ii) I/O port, UART iii) on-chip clocking to provide a range of frequencies , iv) RISC as well as controller concepts.  ...  The whole design is captured using VHDL language and is implemented on FPGA chip using Xilinx .The chip has less hardware complexity as this works based on single addressing mode to access the data for  ... 
doi:10.5121/ijcnc.2010.2409 fatcat:g3mhpwu7lfeebb4coootw3ln6a

Low-power design for embedded processors

B. Moyer
2001 Proceedings of the IEEE  
Opportunities for power optimization and tradeoffs emphasizing low power are available across the entire design hierarchy.  ...  A review of low-power techniques applied at many levels of the design hierarchy is presented, and an example of low-power processor architecture is described along with some of the design decisions made  ...  Differential signaling typically consumes static power, thus the power savings due to a differential clock network are dependent on the operating frequency of the clock and the load being driven.  ... 
doi:10.1109/5.964439 fatcat:pupwsdnz4jfnxfcurl364h2yy4

CHARSTAR

Gokul Subramanian Ravi, Mikko H. Lipasti
2017 SIGARCH Computer Architecture News  
The CHARSTAR design is further optimized for balanced spatiotemporal reconfiguration and also enables efficient joint control of resource and frequency scaling.  ...  Resource gating decisions are cognizant of the power consumed by each node in the clock hierarchy and additionally, entire branches of the clock tree are greedily shut down whenever possible.  ...  ACKNOWLEDGEMENTS The authors would like to thank anonymous reviewers for their insights and comments, Essan Swain for relevant CRIB RTL design and Michael Mishkin for CRIB topology generation, all of which  ... 
doi:10.1145/3140659.3080212 fatcat:wylho4k46ffcxdm65xf4lrjvla

Instruction set architectural guidelines for embedded packet-processing engines

Mostafa E. Salehi, Sied Mehdi Fakhraie, Amir Yazdanbakhsh
2012 Journal of systems architecture  
His research interests include novel techniques for high-speed digital design, low-power logic design, and system integration of networking devices.  ...  In this domain, the growing demands for higher bandwidth and performance besides the ongoing development of new networking protocols and applications call for flexible power-and performance-optimized engines  ...  However, because of the complexity of these instructions, they would complicate the pipeline design and hence, might elongate the overall clock period of the processor.  ... 
doi:10.1016/j.sysarc.2012.02.004 fatcat:jzaqkm5jejdpxmlory3ee4ljgy

Practical Full Chip Clock Distribution Design with a Flexible Topology and Hybrid Metaheuristic Technique

Eng Keong Teh, Mohamad Adzhar Md Zawawi, Mohamed Fauzi Packeer Mohamed, Nor Ashidi Mat Isa
2021 IEEE Access  
This article recommends a practical technique to design full chip (FC) clock tree of a complex system-on-chip (SoC).  ...  Our work on a 10nm SoC product showed that the topology and algorithm managed to produce averagely 16.98% better global skew, 42.75% less divergence on critical clock paths and with 64.5% shorter clock  ...  Tan, James Lim, Wen Chin Lim, Roberto Perez, Jugantor Chetia, Kah Weng Ng, Boon Phin Tan, Pik Lay Teo, and people whom had helped or shared helpful information with him on the artificial intelligent algorithm  ... 
doi:10.1109/access.2021.3053052 fatcat:t77esjo2gzbgzh5rwbci7sjgmy

CRC – Concepts and Evaluation of Processor-Like Reconfigurable Architectures (CRC – Konzepte und Bewertung prozessorartig rekonfigurierbarer Architekturen)

Tobias Oppold, Thomas Schweizer, Julio Oliveira Filho, Sven Eisenhardt, Wolfgang Rosenstiel
2007 it - Information Technology  
The CRC project focuses on the utilization of fast reconfiguration to optimize area, performance, and power.  ...  This article provides an overview of the optimization techniques and a summary of current evaluation results.  ...  One clock cycle later, operations 3 and 4 work on their parts of input vector n and operations 9-12 work on input vector n -1, etc.  ... 
doi:10.1524/itit.2007.49.3.157 fatcat:w2sx64up6vdsxbogjb2qe634gi

An integrated hardware/software design methodology for signal processing systems

Lin Li, Carlo Sau, Tiziana Fanni, Jingui Li, Timo Viitanen, François Christophe, Francesca Palumbo, Luigi Raffo, Heikki Huttunen, Jarmo Takala, Shuvra S. Bhattacharyya
2019 Journal of systems architecture  
As a demonstration of the proposed design framework, we present a dataflow-based deep neural network (DNN) implementation for vehicle classification that is streamlined for real-time operation on embedded  ...  for design and implementation of signal processing systems on system-onchip (SoC) platforms.  ...  the Sardinian Regional Project PROSSIMO (POR FESR 2014/20-ASSE I).  ... 
doi:10.1016/j.sysarc.2018.12.010 fatcat:owkfwvndxbcqzpukk3v4i63ine

CLOCK DISTRIBUTION NETWORKS WITH GRADUAL SIGNAL TRANSITION TIME RELAXATION FOR REDUCED POWER CONSUMPTION

SHERIF A. TAWFIK, VOLKAN KURSUN
2008 Journal of Circuits, Systems and Computers  
The new methodology employs nonuniform buffer insertion and progressive relaxation of the transition time requirements from the leaves to the root of the clock distribution network.  ...  Clock distribution network consumes a significant portion of the total chip power since the clock signal has the highest activity factor and drives the largest capacitive load in a synchronous integrated  ...  Restricting the buffer insertion to be performed only at the beginning of each branch produces a sub-optimal design.  ... 
doi:10.1142/s0218126608004824 fatcat:7w46bmdcbbbonlvvz5wtd66ufe
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