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Integrating RTL IPs into TLM designs through automatic transactor generation

Nicola Bombieri, Nicola Deganello, Franco Fummi
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
In this paper we present a methodology to automatically generate transactors for RTL IPs. We show how the transactor code can be automatically generated by exploiting the testbench of any RTL IP.  ...  Nevertheless, transactors implementation is still manual, tedious and error-prone, and the effort spent to verify their correctness often overcomes the benefits of the TLM-based design flow.  ...  Acknowledgments The authors would like to thank Andrea Fedeli of STMicroelectronics for providing the case study and supporting the analysis of the application results.  ... 
doi:10.1145/1403375.1403382 fatcat:u6swmsuapvhqnmknlqcow3sjcy

Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation

Nicola Bombieri, Nicola Deganello, Franco Fummi
2008 2008 Design, Automation and Test in Europe  
In this paper we present a methodology to automatically generate transactors for RTL IPs. We show how the transactor code can be automatically generated by exploiting the testbench of any RTL IP.  ...  Nevertheless, transactors implementation is still manual, tedious and error-prone, and the effort spent to verify their correctness often overcomes the benefits of the TLM-based design flow.  ...  Acknowledgments The authors would like to thank Andrea Fedeli of STMicroelectronics for providing the case study and supporting the analysis of the application results.  ... 
doi:10.1109/date.2008.4484653 dblp:conf/date/BombieriDF08 fatcat:j74ryrpslneadfxklh4uvst2gu

Automatic generation of systemc transactors from graphical FSM

Tareq Hasan Khan, Sofiene Tahar, Otmane Ait Mohamed, Ali Habibi
2007 2007 Internatonal Conference on Microelectronics  
We also define a methodology and a tool that automatically generates SystemC TLM-RTL transactors from these AsmL specifications.  ...  The SoC design flow consists of different levels of abstraction. At Transaction Level Modeling (TLM) different modules communicate with each other through function calls.  ...  Hence, it presents a critical limitation of the use of transactors in the SystemC design flow only at RTL.  ... 
doi:10.1109/icm.2007.4497706 fatcat:pbced4uqongdjjuh6zpafusp5i

Embedded software development on top of transaction-level models

Wolfgang Klingauf, Robert Günzel, Christian Schröder
2007 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '07  
To this end, a lightweight HPC protocol is presented, and we propose a method to generate the infrastructure for HPC communication from a straightforward input description.  ...  But the proposed APIs only provide low-level read/write operations via a TLM interconnect.  ...  RELATED WORK TLM-based HW-SW co-design with a general-purpose system level design language (SLDL) such as SystemC or SpecC is generally seen as the state-of-the-art in embedded system design.  ... 
doi:10.1145/1289816.1289827 dblp:conf/codes/KlingaufGS07 fatcat:ayvgvxnmrrfs7hb4sjwcsiszu4

On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL

N. Bombieri, F. Fummi, G. Pravadelli
2006 Proceedings of the Design Automation & Test in Europe Conference  
It allows the designers to focus on the functionality of the design, while abstracting away implementation details that will be added at lower abstraction levels.  ...  Transaction level modeling (TLM) is becoming an usual practice for simplifying system-level design and architecture exploration.  ...  The TLM design is refined in an equivalent RTL module by following a standard semi-automatic TLM design flow.  ... 
doi:10.1109/date.2006.243898 dblp:conf/date/BombieriFP06 fatcat:bwcfhai3tjeqdfewc4tqn53qxe

Synthesis of optimized hardware transactors from abstract communication specifications

Dongwook Lee, Hyungman Park, Andreas Gerstlauer
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
To address this challenge, we present a design flow for automatic synthesis of hardware transactors, which realize abstractly specified communication semantics on top of protocol-level transactions.  ...  The flow supports a generic set of communication semantics and target implementations, where transactors are custom-generated for a specific application and architecture combination.  ...  Solely targeting design space exploration, several approaches support the automatic generation of TLMs for early prototyping and validation, but without the capability to generate actual implementations  ... 
doi:10.1145/2380445.2380508 dblp:conf/codes/LeePG12 fatcat:m3taxwwyc5at7oxrviossunbza

Maintaining consistency between systemC and RTL system designs

Alistair Bruce, M. M. Kamal Hashmi, Andrew Nightingale, Steve Beavis, Nizar Romdhane, Christopher Lennard
2006 Proceedings of the 43rd annual conference on Design automation - DAC '06  
The configuration of the verification testbench is kept consistent with the design by using system-design meta-data described using the specifications of The SPIRIT Consortium.  ...  This enables a single test-bench to be applied for systems modeled both in SystemC, as well as at the RT level.  ...  Transactors for Standard TLM Interfaces For SystemC modeling, the transactors are generated with a method-calling interface for each level of abstraction.  ... 
doi:10.1145/1146909.1146936 dblp:conf/dac/BruceHNBRL06 fatcat:uuys6vtjyzegtlvgdjr3kdz43e

Maintaining consistency between SystemC and RTL system designs

A. Bruce, A. Nightingale, N. Romdhane, M.M.K. Hashmi, S. Beavis, C. Lennard
2006 Proceedings - Design Automation Conference  
The configuration of the verification testbench is kept consistent with the design by using system-design meta-data described using the specifications of The SPIRIT Consortium.  ...  This enables a single test-bench to be applied for systems modeled both in SystemC, as well as at the RT level.  ...  Transactors for Standard TLM Interfaces For SystemC modeling, the transactors are generated with a method-calling interface for each level of abstraction.  ... 
doi:10.1109/dac.2006.229178 fatcat:jng6yx5utfgtnnqie6jm2yho7e

Virtual Prototyping of Embedded Platforms for Wireless and Multimedia

T. Kogel, M. Braun
2006 Proceedings of the Design Automation & Test in Europe Conference  
We believe that one of the major obstacles preventing the urgently required adoption and proliferation of an ESL based design approach is the nonexistence of an efficient and intuitive methodology for  ...  This extended abstract gives a rough overview of a modeling methodology we have developed on the basis of SystemC based Transaction Level Modeling (TLM) in order to remedy this lack of modeling competence  ...  TLM based ESL design flow When designing an SoC the selection of a design flow is dependent on the design tasks that will be needed. An example design flow is depicted in figure 1.  ... 
doi:10.1109/date.2006.243856 dblp:conf/date/KogelB06 fatcat:u3ip3l24pfhsjpqyww5rl7hiiq

Assertion-Based Functional Consistency Checking between TLM and RTL Models

Mingsong Chen, Prabhat Mishra
2013 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems  
Transaction Level Modeling (TLM) is promising for functional validation at an early stage of System-on-Chip (SoC) design.  ...  The experimental results using several industrial designs demonstrate that our method can automatically check the functional consistency between different abstraction levels.  ...  [10] proposed a transactor-based dynamic verification method. By using transactors, the TLM testbenches can be reused during the TLM-RTL co-simulation.  ... 
doi:10.1109/vlsid.2013.208 dblp:conf/vlsid/ChenM13 fatcat:whpltsrfvvgnvhyojsh37df3au

Integrated Design Environment for Reconfigurable HPC [chapter]

Lilian Janin, Shoujie Li, Doug Edwards
2010 Lecture Notes in Computer Science  
Its co-simulation capabilities and the automatic regeneration of interfaces allow an incremental design strategy in which the HPC programmer co-designs both software and hardware on the host.  ...  The whole design including the generated interfaces is visible in a graphical view with real-time representation of simulation events for debugging purpose.  ...  We would like to express our thanks to the CCLRC Daresbury Laboratory and their great team for providing access to their Cray XD1.  ... 
doi:10.1007/978-3-642-12133-3_41 fatcat:zluo3gxrozfgte3q4syddbw2du

The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems

Diego Braga, Franco Fummi, Graziano Pravadelli, Sara Vinco
2012 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)  
Furthermore, UNIVERCM allows to generate a homogeneous representation of the components behavior (in a bottom-up flow) to allow simulation and validation of the generated components and of the final system  ...  The former is an IEEE standard for specifying interface and communication style of digital IPs.  ...  ACKNOWLEDGEMENTS The authors thank Dr. Wolfgang Müller (Universität Paderborn) for having provided both the Eclipse-based editor for IP-XACT and the experimental case studies.  ... 
doi:10.1109/hldvt.2012.6418246 dblp:conf/hldvt/BragaFPV12 fatcat:p7rkkvohazbdzj6quvejnfmjku

HIFSuite: Tools for HDL Code Conversion and Manipulation

Nicola Bombieri, Giuseppe Di Guglielmo, Michele Ferrari, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Alessandro Venturelli
2010 EURASIP Journal on Embedded Systems  
Moreover, HIFSuite includes tools, which rely on HIF APIs, for manipulating HIF descriptions in order to support code abstraction/refinement and postrefinement verification.  ...  The core of HIFSuite is the HDL Intermediate Format (HIF) language upon which a set of front-end and back-end tools have been developed to allow the conversion of HDL code into HIF code and vice versa.  ...  Then, the automatic transactor generation has been instantaneously accomplished by the TGEN tool. On the other hand, 3 days/man have been spent for manually implementing the four transactors.  ... 
doi:10.1155/2010/436328 fatcat:3lr56i2jujardauodjsgvg3qei

Incremental ABV for Functional Validation of TL-to-RTL Design Refinement

Nicola Bombieri, Franco Fummi, Graziano Pravadelli
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
However, its introduction arouses a new challenge for designers and verification engineers, since there are no mature tools to automatically synthesize an RTL implementation from a transaction-level (TL  ...  Transaction-level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems.  ...  Figure 1 : 1 TLM/ABV design and verification flow. Figure 2 : 2 Proposed Incremental ABV methodology. Figure 3 : 3 The role of the transactor in assertion reuse.  ... 
doi:10.1109/date.2007.364404 dblp:conf/date/BombieriFP07 fatcat:5nowcv3bizdf7pestkrmhse4bi

ESL design and HW/SW co-verification of high-end software defined radio platforms

A. C. H. Ng, J. W. Weijers, M. Glassee, T. Schuster, B. Bougard, L. Van der Perre
2007 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '07  
This paper demonstrates an integrated ESL design flow built on advanced ESL tools to design SDR platforms for handhelds.  ...  Incremental RTL verification based on co-simulation and co-emulation is also presented.  ...  The proposed design flow starts with creating a high level SystemC TLM model (Phase 1). Figure 2 outlines the design methodology of the HW/SW co-verification flow.  ... 
doi:10.1145/1289816.1289864 dblp:conf/codes/NgWGSBP07 fatcat:i76lkw33anhcllhiq3vtlb2z3y
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