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On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment

Xiao Liu, Qiang Xu
2009 2009 International Test Conference  
In this work, we propose a generic framework for test power reduction in linear decompressor-based test compression environment, which is able to effectively reduce shiftand capture-power simultaneously  ...  Growing test data volume and excessive test power consumption in scan-based testing are both serious concerns for the semiconductor industry.  ...  Meng-Fan Wu and Prof. Jiun-Lang Huang from National Taiwan University for providing the test cubes and their X-filling results.  ... 
doi:10.1109/test.2009.5355554 dblp:conf/itc/LiuX09 fatcat:yahdk5szwjdlhmsq5s52djdxfi

Compression-Friendly Low Power Test Application Based on Scan Slices Reusing

Weizheng Wang, JinCheng Wang, Shuo Cai, Wei Su, Lingyun Xiang
2016 JSTS Journal of Semiconductor Technology and Science  
This paper presents a compression-friendly low power test scheme in EDT environment.  ...  The proposed approach exploits scan slices reusing to reduce the switching activity during shifting for test scheme based on linear decompressor.  ...  The solution in [24] is based on scan block compatibility in each scan chain for shift and capture power reduction.  ... 
doi:10.5573/jsts.2016.16.4.463 fatcat:6a3imw4cvra7vdlrvrws7n3tiq

Low Power Test-Compression for High Test-Quality and Low Test-Data Volume

Vasileios Tenentes, Xrysovalantis Kavousianos
2011 2011 Asian Test Symposium  
In addition, low power decompression needs additional control data which increase the overall volume of test data to be encoded and inevitably increase the volume of compressed test data.  ...  Test data decompressors targeting low power scan testing introduce significant amount of correlation in the test data and thus they tend to adversely affect the coverage of unmodeled defects.  ...  When this pseudorandom scheme is combined with linear and symbol-based decompressors it achieves a significant reduction of the volume of compressed test data as it eliminates the need for controlling  ... 
doi:10.1109/ats.2011.75 dblp:conf/ats/TenentesK11 fatcat:wpd7cu6q2ra2vf7jdqhqeoikha

A scan shifting method based on clock gating of multiple groups for low power scan testing

Sungyoul Seo, Yong Lee, Joohwan Lee, Sungho Kang
2015 Sixteenth International Symposium on Quality Electronic Design  
Keywords Scan-based testing, low power scan testing, shifting power reduction, design-for-testability (DFT)  ...  Experimental results on ITC'99 benchmark circuits and industrial circuits show that this shifting method reduces the scan shifting power in all cases.  ...  Under the scan-based testing, the two problems are incurred: shifting power and capture power.  ... 
doi:10.1109/isqed.2015.7085417 dblp:conf/isqed/Seo0LK15 fatcat:2b45mxa7dndl3oembfcsoqhefi

High-Quality Statistical Test Compression With Narrow ATE Interface

Vasileios Tenentes, Xrysovalantis Kavousianos
2013 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified  ...  Index Terms-Defect-oriented testing, design for testability, dft, IP cores, low-power scan-based testing, multi-core SoC, selective Huffman, test data compression, unmodeled defect coverage.  ...  Specifically, in [33] , a shadow register is utilized to offer low-power shift testing by repeating test data, while in [34] , selective scan enable deactivation is used for low capture power.  ... 
doi:10.1109/tcad.2013.2256394 fatcat:4h5veccv5bcxxgugetmdry2qgi

Capture-power-aware test data compression using selective encoding

Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu
2011 Integration  
The "don't-care" bits (also known as X-bits) in given test cube can be exploited for test data compression and/or test power reduction, and these techniques may contradict to each other because the very  ...  This paper proposes a capture-power-aware test compression scheme that is able to keep capture-power under a safe limit with low test compression ratio loss.  ...  nonlinear code-based schemes that use data compression codes to encode test cubes; (ii) linear decompressor-based schemes that decompress the data using linear operations (e.g., XOR network and/or linear  ... 
doi:10.1016/j.vlsi.2011.01.005 fatcat:7nu27lwddfcuxowf5os7u6urtu

Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets

Xrysovalantis Kavousianos, Vasileios Tenentes, Krishnendu Chakrabarty, Emmanouil Kalligeros
2011 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we present a new defect-oriented dynamic LFSR reseeding technique for test-data compression.  ...  The proposed technique is based on a new output-deviation metric for grading stuck-at patterns derived from LFSR seeds.  ...  Manuscript Test-data compression methods are mainly based on linear decompressors [1] , [3] - [9] , [11] , [12] , [14] .  ... 
doi:10.1109/tvlsi.2010.2079961 fatcat:evbyhphlsnc4rluzu765f3xx2m

Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging

Muhammad Yasin, Ozgur Sinanoglu, Jeyavijayan Rajendran
2017 IEEE Transactions on Information Forensics and Security  
HackTest applies to all existing camouflaged gate-selection techniques and is successful even in the presence of state-of-the-art test infrastructure, i.e. test data compression circuits.  ...  In this paper, we present HackTest, an attack that extracts secret information generated in the test data, even if the test data does not explicitly contain the secret.  ...  Various test compression schemes are available, which include code-based and linear schemes [22] . Linear schemes employ only XOR-networks and Linear Feedback Shift Registers (LFSRs).  ... 
doi:10.1109/tifs.2017.2710954 fatcat:nos73abeyrccdd2lb7lokct5tm

Architecture for integrated test data compression and abort-on-fail testing in a multi-site environment

E. Larsson
2008 IET Computers & Digital Techniques  
compression and abort-on-fail testing at clock-cycle granularity is proposed, and hence both ATE memory reduction and test application time minimisation are addressed.  ...  In contrast with existing approaches, which address either test data compression for ATE memory reduction or abort-on-fail testing for test time minimisation, an architecture that supports both test data  ...  The architecture allows simultaneous test data compression and abort-fail-testing. It also allows simultanous test data compression and diagnosis.  ... 
doi:10.1049/iet-cdt:20070078 fatcat:4vi24fmqsnbrlpq6oyjxqtepxq

A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing

Saman Kiamehr, Farshad Firouzi, Mehdi B. Tahoori
In this paper, we propose a Linear Programming-based X-filling approach to minimize PSN in at-speed scan test by assigning appropriate values to X-bits in partially specified test patterns.  ...  In this paper, spatial and transition time correlations due to circuit layout, power mesh, and netlist are taken into account to increase the accuracy of dynamic PSN estimation and for the first time the  ...  An X-filling-based technique is presented in [7] to generate test patterns with low launch cycle power supply noise in the linear decompressor-based test pattern compression environment.  ... 
doi:10.1109/ets.2013.6569356 dblp:conf/ets/KiamehrFT13 fatcat:6i5ys3qbwfgh3kkca43kugc44a

Experimental Study on Machine Learning with Approximation to Data Streams

Zhang Fu, Jiani Jiang
2019 2019 Sixth International Conference on Internet of Things: Systems, Management and Security (IOTSMS)  
Enclosed Environment This project is implemented and evaluated in an enclosed virtual environment.  ...  In the second test scenario, the results show the common linear growth trend on linear regression, random forest and k-NN. But random forest performs better than the other two.  ... 
doi:10.1109/iotsms48152.2019.8939225 dblp:conf/iotsms/FuJ19 fatcat:gy65ekyqyzfkdotycqnxqfojyy

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Zhanglei Wang, K. Chakrabarty, Seongmoon Wang
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
An efficient linear feedback shift register (LFSR) reseeding technique is used as the compression engine. All cores on the SOC share a single on-chip LFSR.  ...  We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper design, and test scheduling.  ...  A single on-chip LFSR-based decompressor is used to feed all cores on the SOC.  ... 
doi:10.1109/tcad.2009.2021731 fatcat:tegxogeexzeybaxkseq6ic4jsi

Single Cycle Access Structure for Logic Test

Tobias Strauch
2012 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
It eliminates the peak power consumption problem of conventional shift-based scan chains and reduces the activity during shift and capture cycles.  ...  The test cycles per net based on a simple test pattern generator algorithm without test pattern compression is below 1 for larger designs and is independent of the design size.  ...  The algorithm in [31] reduces switching activity during scan testing (test vectors of Table III of [31] are taken) and simultaneous test time and power reduction are shown in [5] (see Table II  ... 
doi:10.1109/tvlsi.2011.2134875 fatcat:aa4him4iszaytada77c2uda5la

The M2DC Project: Modular Microserver DataCentre

Mariano Cecowski, Giovanni Agosta, Ariel Oleksiak, Michal Kierzynka, Micha vor dem Berge, Wolfgang Christmann, Stefan Krupop, Mario Porrmann, Jens Hagemeyer, Rene Griessl, Meysam Peykanu, Lennart Tigges (+13 others)
2016 2016 Euromicro Conference on Digital System Design (DSD)  
Since their introduction, FPGAs can be seen in more and more different fields of applications.  ...  This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.  ...  The complexity of the test scenario can include the design of a whole system level environment in order to ensure the correct behavior of the tested device.  ... 
doi:10.1109/dsd.2016.76 dblp:conf/dsd/CecowskiAOKBCKP16 fatcat:bu4nbkqaejebjafrotibui6mkq

Forensic Discrimination between Traditional and Compressive Imaging Systems [article]

Ali Taimori, Farokh Marvasti
2018 arXiv   pre-print
To do this, we first mathematically and systematically model the imaging system based on compressive sensing technology.  ...  In this regards, one of basic scenarios in image forensics is to distinguish traditionally sensed images from sophisticated compressively sensed ones.  ...  Amini and other researchers in Signal Processing and Multimedia Lab for their valuable comments.  ... 
arXiv:1811.03157v1 fatcat:vpdeqxkqrnbn5ctatpaepqlo3m
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