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On multiplexed signal tracing for post-silicon debug

Xiao Liu, Qiang Xu
2011 2011 Design, Automation & Test in Europe  
Existing techniques typically trace the same set of signals throughout each debug run, which is not quite effective for catching design errors.  ...  Trace-based debug solutions facilitate to eliminate design errors escaped from pre-silicon verification and have gained wide acceptance in the industry.  ...  One effective post-silicon debug technique is to monitor and trace the behavior of the circuit under debug (CUD) during its normal operation.  ... 
doi:10.1109/date.2011.5763116 dblp:conf/date/LiuX11 fatcat:kmdrmunpnraw3eeb3iohjd7key

On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation

Xiao Liu, Qiang Xu
2008 2008 17th Asian Test Symposium  
One of the main difficulties in post-silicon validation is the limited debug access bandwidth to internal signals.  ...  In this paper, we propose to reuse these precious TAM resources for real-time debug data transfer in post-silicon validation.  ...  ., Ltd. for his insightful comments to this work.  ... 
doi:10.1109/ats.2008.83 dblp:conf/ats/LiuX08 fatcat:kgpiuchbf5bf5dtmp5uolxacye

On signal tracing in post-silicon validation

Qiang Xu, Xiao Liu
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
Tracing internal signals during circuit's normal operation, being able to provide real-time visibility to the circuit under debug (CUD), is one of the most effective silicon debug techniques and has gained  ...  Trace-based debug solution, however, involves non-trivial design for debug overhead. How to conduct signal tracing effectively for bug elimination is therefore a challenging task for IC designers.  ...  Design Phase Post-silicon Debug Phase Analysis Phase Y N Y Run post-silicon analysis Insert DfD Hardware Transfer data through trace port Store data in trace buffer Fig. 4.  ... 
doi:10.1109/aspdac.2010.5419883 dblp:conf/aspdac/XuL10 fatcat:5ftlnjsgmbf6ro5vvlufbfvnhq

A New Post-Silicon Debug Approach Based on Suspect Window

Jianliang Gao, Yinhe Han, Xiaowei Li
2009 2009 27th IEEE VLSI Test Symposium  
It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observability of the internal signals.  ...  Then we introduce "suspect window" and present a method for determining its boundary. Based on suspect window, we propose a debug approach to achieve high observability by reusing scan chain.  ...  Reusing scan chain is a common technique to improve observability of internal signals in post-silicon debug [5] .  ... 
doi:10.1109/vts.2009.35 dblp:conf/vts/GaoHL09 fatcat:xlmjqmiu4jbgbchalql6b6nsw4

Leveraging reconfigurability to raise productivity in FPGA functional debug

Z. Poulos, Yu-Shen Yang, J. Anderson, A. Veneris, Bao Le
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
In essence, with a single execution of the synthesis flow, the new approach permits a large number of internal signals to be traced for an arbitrary number of clock cycles using a limited number of external  ...  We propose new hardware and software techniques for FPGA functional debug that leverage the inherent reconfigurability of the FPGA fabric to reduce functional debugging time.  ...  In the following discussion, the notation, m-w, represents the tracing setting where m signals are candidates for tracing and w signals are traced concurrently in one silicon execution.  ... 
doi:10.1109/date.2012.6176481 dblp:conf/date/PoulosYAVL12 fatcat:mkqewn5nc5blrab4dcg2la4nh4

Interconnection fabric design for tracing signals in post-silicon validation

Xiao Liu, Qiang Xu
2009 Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09  
These trace signals need to be transferred to on-chip buffers and/or off-chip trace ports for analysis.  ...  One effective technique that provides real-time visibility to the circuit under debug (CUD) is to monitor and trace internal signals during its normal operation.  ...  Multiplexer Network for Mutually-Exclusive Signals Firstly, we need to determine which tapped signals are highlycorrelated and hence may need to be traced together in post-silicon validation.  ... 
doi:10.1145/1629911.1630006 dblp:conf/dac/LiuX09 fatcat:quzfhmwwqrhbvmj7xuykgoib34

Automated Post-Silicon Debugging of Failing Speedpaths

Mehdi Dehbashi, Gorschwin Fey
2012 2012 IEEE 21st Asian Test Symposium  
Then, our automated debugging based on Boolean Satisfiability (SAT) diagnoses speedpaths. The experimental results show the effectiveness of our approach on ISCAS'85 and ISCAS'89 benchmarks suites.  ...  Debugging of speed-limiting paths (speedpaths) is a key challenge in development of Very-Large-Scale Integrated (VLSI) circuits as timing variations induced by process and environmental effects are increasing  ...  In a simulation tool, the value of signal c 1 at one time step ago can be found on the successor signal c 2 . A multiplexer is added to select c 1 or c 2 . The multiplexer delay is zero.  ... 
doi:10.1109/ats.2012.42 dblp:conf/ats/DehbashiF12 fatcat:3yylfq272vfu7mg5wbhcirkjdm

A case study of Time-Multiplexed Assertion Checking for post-silicon debugging

Ming Gao, Kwang-Ting Cheng
2010 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)  
In this paper, we present a design-for-debug (DfD) techniquenamed Time-Multiplexed Assertion Checking (TMAC) --for post-silicon bug detection and isolation.  ...  Post-silicon debugging has become the least predictable and most labor-intensive step in the modern design flow at 65nm and below.  ...  The authors also acknowledge the support of the Gigascale Systems Research Center (GSRC), one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation  ... 
doi:10.1109/hldvt.2010.5496657 dblp:conf/hldvt/GaoC10 fatcat:df2ytxj3b5gyzi4mczpimnqpkm

Automated Debugging from Pre-Silicon to Post-Silicon [chapter]

Mehdi Dehbashi, Görschwin Fey
2014 Debug Automation from Pre-Silicon to Post-Silicon  
The experimental results show the effectiveness of the approach in post-silicon debugging.  ...  This paper presents a generalized approach to automate debugging which can be used in different scenarios from design debugging to post-silicon debugging.  ...  The main challenge of post-silicon debugging is the limited observation of internal signals.  ... 
doi:10.1007/978-3-319-09309-3_4 fatcat:5vn3vvmc6bbydaen4t6v66bxum

Automated debugging from pre-silicon to post-silicon

Mehdi Dehbashi, Gorschwin Fey
2012 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)  
The experimental results show the effectiveness of the approach in post-silicon debugging.  ...  This paper presents a generalized approach to automate debugging which can be used in different scenarios from design debugging to post-silicon debugging.  ...  The main challenge of post-silicon debugging is the limited observation of internal signals.  ... 
doi:10.1109/ddecs.2012.6219082 dblp:conf/ddecs/DehbashiF12 fatcat:q4xqraylffdanhhqdfh3dgm2q4

Dynamic Selection of Trace Signals for Post-Silicon Debug

Kanad Basu, Prabhat Mishra, Priyadarsan Patra, Amir Nahir, Alon Adir
2013 2013 14th International Workshop on Microprocessor Test and Verification  
A major challenge in post-silicon debug is limited observability of the internal signals. Existing approaches address this issue by selecting a small set of useful signals.  ...  Post-silicon validation is one of the most expensive and complex tasks in today's System-on-Chip (SoC) design methodology.  ...  We choose three circuits for our purpose, namely RS232 Uart, OPB Onewire and i2cslave. These will be referred to as uart, one and slave, respectively for further discussion in this section.  ... 
doi:10.1109/mtv.2013.13 dblp:conf/mtv/BasuMPNA13 fatcat:e4mjrqvjmbajrcqhf76g4e3ody

Extending trace history through tapered summaries in post-silicon validation

Sandeep Chandran, Preeti Ranjan Panda, Deepak Chauhan, Sharad Kumar, Smruti R. Sarangi
2016 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)  
On-chip trace buffers are increasingly being used for at-speed debug during post-silicon validation. However, the activity history captured by these buffers is small due to their limited size.  ...  We demonstrate the usefulness of the proposed methodology for debugging various classes of bugs encountered during post-silicon validation.  ...  However, the limited size of these on-chip trace buffers poses a significant challenge to post-silicon debug because only a short history of the activity inside a chip is captured, and the captured traces  ... 
doi:10.1109/aspdac.2016.7428099 dblp:conf/aspdac/ChandranPCKS16 fatcat:zlru6kndjvdk3a42kb7qvv63c4

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment

Yu-Shen Yang, Andreas Veneris, Nicola Nicolici
2012 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Embedded hardware blocks, such as scan chains and trace buffers, provide a means to acquire data of internal signals in real time for debugging.  ...  It also introduces a technique to automate the configuration process for trace-buffer based hardware in order to acquire helpful information for debugging the failure.  ...  Those pre-selected signals are divided into groups and connected to the on-chip memory through a multiplexer. During execution, only one group can be traced at a time.  ... 
doi:10.1109/tvlsi.2011.2142407 fatcat:ilk3jgovmvggroaq24idwtxwha

A Novel Post-Silicon Debug Mechanism Based on Suspect Window

Jianliang GAO, Yinhe HAN, Xiaowei LI
2010 IEICE transactions on information and systems  
It is imperative to identify the bugs as soon as possible through post-silicon debug. For post-silicon debug, observability is one of the biggest challenges.  ...  Based on Suspect Window, we propose a novel debug mechanism to locate the bug both temporally and spatially.  ...  Post-silicon debug (simplified as silicon debug in the following) needs to identify both functional bugs and electrical bugs (e.g. [5] , [6] ).  ... 
doi:10.1587/transinf.e93.d.1175 fatcat:d3ygiydqgrgrlbeu5l3hpormea

Post-silicon verification and debugging with control flow traces and patchable hardware

Masahiro Fujita
2012 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)  
These analysis give information on how messages are transferred onto NoC, which are to be used for post-silicon analysis.  ...  From the monitoring results, control sequences on interactions of cores are automatically determined to be used for post-silicon analysis.  ...  POST-SILICON VERIFICATION BY TRACING/ANALYZING COMMUNICATIONS AMONG CORES Here we introduce a method for debugging communications in SoCs at transaction level [2] .  ... 
doi:10.1109/hldvt.2012.6418250 dblp:conf/hldvt/Fujita12 fatcat:unnymogrqvfa5mvbftecngryyq
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