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A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors

Anderson L. Sartor, Arthur F. Lorenzon, Luigi Carro, Fernanda Kastensmidt, Stephan Wong, Antonio C. S. Beck
2015 2015 IEEE Computer Society Annual Symposium on VLSI  
In this scenario, our work proposes two new low overhead fault tolerance approaches, with zero latency detection, that correct soft errors in the pipelines of a configurable VLIW processor.  ...  We compared our approach to related work and demonstrate that we are more efficient when one considers the area, performance, power dissipation and error coverage altogether.  ...  It is implemented on an 8-issue processor that can have a variable number of duplicated instructions depending on the application phase: between zero (no fault tolerance) and four (full duplication).  ... 
doi:10.1109/isvlsi.2015.19 dblp:conf/isvlsi/SartorLCKWB15 fatcat:hretbqxirfcctcnfpwyf62mbke

A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip

G. Beltrame, C. Bolchini, L. Fossati, A. Miele, D. Sciuto
2007 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)  
. 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 1550-5774/07 $25.00  ...  and tolerance issues.  ...  The second module accesses a repository where various techniques (acting on the hardware as well as on the software) for guaranteeing fault detection/tolerance properties are stored.  ... 
doi:10.1109/dft.2007.35 dblp:conf/dft/BeltrameBFMS07 fatcat:by3mdg7yjjafvizv652ar5vnlq

Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-Issue VLIW Processor

Anderson L. Sartor, Pedro H. E. Becker, Joost Hoozemans, Stephan Wong, Antonio C. S. Beck
2018 IEEE Transactions on Multi-Scale Computing Systems  
Based on that, we propose a new VLIW-based processor design capable of adapting the execution of the application at run-time in a totally transparent fashion, considering performance, fault tolerance,  ...  In the design of modern-day processors, energy consumption and fault tolerance have gained significant importance next to performance.  ...  The fault-tolerant mode (1) is automatic and always on.  ... 
doi:10.1109/tmscs.2017.2760299 fatcat:rdfosxr3engn7pgg3cpnp57i6q

Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors

Anderson L. Sartor, Arthur F. Lorenzon, Luigi Carro, Fernanda Kastensmidt, Stephan Wong, Antonio C. S. Beck
2017 ACM Journal on Emerging Technologies in Computing Systems  
In this scenario, our work proposes three low overhead fault tolerance approaches based on instruction duplication with zero latency detection, which uses a rollback mechanism to correct soft errors in  ...  the pipelanes of a configurable VLIW processor.  ...  To harden the processor against such errors, fault-tolerant techniques are mandatory Authors' addresses: A. L. Sartor, A. F. Lorenzon, L. Carro, F. Kastensmidt, and A. C. S.  ... 
doi:10.1145/3001935 fatcat:kayy4n7teje2lkpua3rjt2jh6q

Toward an integrated design methodology for fault-tolerant, multiple clock/voltage integrated systems

R. Marculescu, D. Marculescu, L. Pileggi
IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.  
To support the proposed methodology, two major issues are of interest: • Fault-tolerant communication schemes and protocols suitable for on-chip implementation and tools for their performance evaluation  ...  This paper introduces the concept of fault-tolerant communication for Multiple Clock/Voltage (MCV) integrated systems.  ...  Essential ingredients for this methodology include fault-tolerant communication and reliance on a globally asynchronous, locally synchronous design style.  ... 
doi:10.1109/iccd.2004.1347917 dblp:conf/iccd/MarculescuMP04 fatcat:o7uko3me35cppjiu3lnvi7a2fu

Reduced Communications Fault Tolerant Task Scheduling Algorithm for Multiprocessor Systems

Nabil Tabba, Reza Entezari-Maleki, Ali Movaghar
2012 Procedia Engineering  
This paper presents a fault tolerant scheduling algorithm for task graph applications in multiprocessor systems.  ...  Fault tolerance is becoming a necessary attribute in multiprocessor systems as the number of processing elements is getting larger.  ...  n pred n l l P r n n c n Proc n FT n w P C P n FT j + + × = + ≤ ≤ ∈ (3) where r(P l ) is the ready time of the processor P l .  ... 
doi:10.1016/j.proeng.2012.01.577 fatcat:myfg54mcerd6ljzdfiayxyzw4e

Parallel fault-tolerant robot control

Deirdre L. Hamilton, John K. Bennett, Ian D. Walker, Jon D. Erickson
1992 Cooperative Intelligent Robotics in Space III  
Most robot controllers today e m p l o y a single processor architecture.  ...  Processor fault tolerance is also made possible by the existence of multiple processors. There is a trade-o between performance and the level of fault tolerance provided.  ...  The use of multiple processors provides fault tolerance via processor redundancy. The failure of one processor, or a few processors, does not result in system failure.  ... 
doi:10.1117/12.131703 fatcat:dvk3omovgvbfjfq456olehwsty

An Efficient Backup-Overloading for Fault-Tolerant Scheduling of Real-Time Tasks [chapter]

R. Al-Omari, G. Manimaran, Arun K. Somani
2000 Lecture Notes in Computer Science  
In this paper, we propose a technique called dynamic grouping, to be used with backup overloading in a primary-backup based fault-tolerant dynamic scheduling algorithm in multiprocessor real-time systems  ...  Tasks corresponding to these applications have deadlines to be met despite the presence of faults.  ...  Therefore, fault tolerance is an important requirement in such systems. Scheduling multiple versions of tasks on di erent processors can provide fault tolerance.  ... 
doi:10.1007/3-540-45591-4_177 fatcat:vkhlgyp7rrawzmjgecbbd2b3n4

A Fault-Tolerant Scheduling Algorithm using Hybrid Overloading Technology for Dynamic Grouping based Multiprocessor Systems

Xing-biao Yu, Jun-suo Zhao, Chang-wen Zheng, Xiao-hui Hu
2014 International Journal of Computers Communications & Control  
In order to extend the application area of fault-tolerant scheduling algorithm based on hybrid overloading for multiprocessor and increase the fault-tolerant number of processors, we propose a new fault-tolerant  ...  In the process of fault-tolerant scheduling the processors are dynamically divided into some groups based on overloading task link, so as to keep good scheduling success ratio and enhance the fault-tolerant  ...  When there is only one processor fault in DG_PB-BB,LG_PB-BB and PB-BB_AP algorithm, the differences of GR for the system of L=0.25,L=0.5 and L=1 are small.  ... 
doi:10.15837/ijccc.2012.5.1358 fatcat:63aoxx2qw5fynpd7tucad6yxyi

A Fault Tolerant Scheduling Heuristics for Distributed Real Time Embedded Systems

Bachir Malika, Hamoudi Kalla
2018 Cybernetics and Information Technologies  
These scheduling heuristics that we propose are redundancy-based software to tolerate hardware faults. We consider only processor permanent failures with a fail-silent behavior.  ...  In this paper, fault tolerant task scheduling algorithms are proposed for mapping task graphs to heterogeneous processing nodes.  ...  K a l l a [1] presents a heuristic called AAA-TB, based on Hybrid redundancy to tolerate arbitrary faults in processors and communication buses in a reactive system.  ... 
doi:10.2478/cait-2018-0038 fatcat:ec7fxlrenzeuvkrunljkizs4l4

Fault tolerance versus performance metrics for robot systems

Deirdre L. Hamilton, Ian D. Walker, John K. Bennett
1996 Reliability Engineering & System Safety  
We show their usefulness using a variety of proposed fault tolerance a p p r oaches in the literature, focusing on multiprocessor control architectures.  ...  The measures, which are designed to evaluate fault tolerance/performance/cost tradeo s, can also be u s e d to evaluate pure p erformance o r p u r e fault tolerance strategies.  ...  Therefore, for our comparisons, we assign an importance of one (k 1 = 1 ) t o t h e f a u l t tolerance ratings.  ... 
doi:10.1016/s0951-8320(96)00041-5 fatcat:oxi5rgiyxfaxlcaq7s6lbw2x6u

On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays

Israel Koren, Melvin A. Breuer
1984 IEEE transactions on computers  
Since various fault-tolerant techniques are possible, we the architecture of a processor array.  ...  However, increased design and implementation of including fault-tolerance in the architecture of a processor costs should be expected when fault-tolerance is being introduced into array.  ...  On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays ISRAEL KOREN, MEMBER, IEEE, AND MELVIN A.  ... 
doi:10.1109/tc.1984.5009312 fatcat:sh5j6ravvbavrmqrya56nrd4ka

Fault Tolerant Algorithms for a Linear Array with a Reconfigurable Pipelined Bus System [chapter]

Anu G. Bourgeois, Jerry L. Trahan
2000 Lecture Notes in Computer Science  
We present some fundamental algorithms that are able to tolerate up to N=2 faults on an N -processor LARPBS one particular optical model.  ...  Reference Bus Select Bus R1 R2 R3 R4 R0 u t Table 1 . t1 Fault Tolerant LARPBS Algorithms Algorithm Time on Faulty Time on Fault-Free No. of Processors median row Olog N O1 ON image  ...  Fault Tolerant Algorithms In this section we describe some basic algorithms for an N-processor LARPBS that can tolerate up to N=2 faults.  ... 
doi:10.1007/3-540-45591-4_144 fatcat:f6z2rm3qsnao7mm2vb6x4gm45m

Tolerating faults in injured hypercubes using maximal fault-free subcube-ring

Yuh-Shyan Chen, Jang-Ping Sheu
1997 Parallel Computing  
To demonstrate the fault-tolerant capability of our approach, we implement two fault-tolerant algorithms, matrix-multiplication and sorting algorithms, on the nCUBE/2E hypercube machine with 32 processors  ...  In addition, Sheu, Chen, and Chang [24] proposed a subcube partitioning method for designing a fault-tolerant sorting algorithm that can tolerate at most n -1 faulty processors on n-dimensional hypercubes  ...  To demonstrate the fault-tolerant capability of our approach, we implement two fault-tolerant algorithms, matrix-multiplication and sorting, on the nCUBe/2E hypercube machines with 32 processors.  ... 
doi:10.1016/s0167-8191(96)00056-7 fatcat:dxmlgnzuundrtjgriyetotd3oy

Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis

Heinz Riener, Stefan Frehse, Gorschwin Fey
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
In this paper, we focus on synthesis techniques to improve the fault tolerance of embedded systems considering hardware and software.  ...  A greedy algorithm is presented which iteratively assesses the fault tolerance of a processor-based system and decides which components of the system have to be hardened choosing from a set of existing  ...  Non-robust instructions have to be executed on robust hardware instances in order to maximize the fault tolerance of the processor-based system.  ... 
doi:10.7873/date.2013.197 dblp:conf/date/RienerFF13 fatcat:xazj7uagibab5bchqpbyipsvqq
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