Filters








1,335 Hits in 6.1 sec

On convergence of switching windows computation in presence of crosstalk noise

Pinhong Chen, Yuji Kukimoto, Chin-Chi Teng, Kurt Keutzer
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
Detecting overlapping of switching windows between coupling nets is a major static technique to accurately locate crosstalk noise.  ...  However, due to the mutual dependency between switching windows, the computation requires iterations to converge.  ...  CONVERGENCE OF SWITCHING WIN-DOWS COMPUTATION In this section, we will argue the convergence of switching windows computation. the aggressor's switching window needs to be extended to infinity such as  ... 
doi:10.1145/505408.505410 fatcat:qgq3ag4epndfdaesxcxlknu3hu

On convergence of switching windows computation in presence of crosstalk noise

Pinhong Chen, Yuji Kukimoto, Chin-Chi Teng, Kurt Keutzer
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
Detecting overlapping of switching windows between coupling nets is a major static technique to accurately locate crosstalk noise.  ...  However, due to the mutual dependency between switching windows, the computation requires iterations to converge.  ...  CONVERGENCE OF SWITCHING WIN-DOWS COMPUTATION In this section, we will argue the convergence of switching windows computation. the aggressor's switching window needs to be extended to infinity such as  ... 
doi:10.1145/505388.505410 dblp:conf/ispd/ChenKTK02 fatcat:4pbnosbsubgsfcdn765xjtnh24

Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise [chapter]

2009 Signal Integrity Effects in Custom IC and ASIC Designs  
In this paper, we present and compare multiple scheduling algorithms to compute switching windows for static timing analysis in presence of crosstalk noise.  ...  Crosstalk effect is crucial for timing analysis in very deep submicron design.  ...  By tracing this envelope waveform, the worst case delay can be obtained. 4 Coupling Delay Computation in Presence of Crosstalk Noise Algorithm In today's technology, RC delay calculation consumes a  ... 
doi:10.1109/9780470546413.ch4 fatcat:mowyf6d73rdx7hs3p7vels6cey

Clock schedule verification with crosstalk

Hai Zhou
2002 Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02  
In this paper, we point out a false negative problem in current clock schedule verification techniques and propose a new approach based on switching windows.  ...  A novel algorithm is given for clock schedule verification in the presence of crosstalk and primary experiments show promising results.  ...  Hassoun for providing the code of their algorithm. This research was supported by a faculty start-up fund from Northwestern University.  ... 
doi:10.1145/589411.589428 dblp:conf/tau/Zhou02 fatcat:fqepx3dzyzep3ajknvc7lxyiym

Clock schedule verification with crosstalk

Hai Zhou
2002 Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02  
In this paper, we point out a false negative problem in current clock schedule verification techniques and propose a new approach based on switching windows.  ...  A novel algorithm is given for clock schedule verification in the presence of crosstalk and primary experiments show promising results.  ...  Hassoun for providing the code of their algorithm. This research was supported by a faculty start-up fund from Northwestern University.  ... 
doi:10.1145/589427.589428 fatcat:bcvwcfksejflvhpaixkgn3n3by

TACO

Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
2000 Proceedings of the 37th conference on Design automation - DAC '00  
The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded.  ...  The methodology utilizes a coupled Ceff gate model for capturing the provably worst-and bestcase delays as a function of the timing-window inputs to the gates.  ...  Acknowledgments The authors would like to thank Alex Suess and Khalid Rahmat from IBM EDA, Fishkill for their help and support in the implementation of TACO in Einstimer and for providing test-case examples  ... 
doi:10.1145/337292.337415 dblp:conf/dac/ArunachalamRP00 fatcat:es6lgt4pinaq3dkivbtz7b4n6m

Timing analysis with crosstalk is a fixpoint on a complete lattice

Hai Zhou
2003 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
However, timing analysis with crosstalk is a mutual dependence problem since the crosstalk effect in turn depends on the timing behavior of a circuit.  ...  Based on that, we prove in general the convergence of any iterative approach. We also show that, starting from different initial solutions, an iterative approach will reach different fixpoints.  ...  Sapatnekar [15] considered the delay computation in the presence of crosstalk for a set of wires within a routing channel.  ... 
doi:10.1109/tcad.2003.816211 fatcat:d6mmn42nybggbcomuvujmpo3vq

Timing analysis with crosstalk as fixpoints on complete lattice

Hai Zhou, Narendra Shenoy, William Nicholls
2001 Proceedings of the 38th conference on Design automation - DAC '01  
However, timing analysis with crosstalk is a mutual dependence problem since the crosstalk effect in turn depends on the timing behavior of a circuit.  ...  Based on that, we prove in general the convergence of any iterative approach. We also show that, starting from different initial solutions, an iterative approach will reach different fixpoints.  ...  Sapatnekar [15] considered the delay computation in the presence of crosstalk for a set of wires within a routing channel.  ... 
doi:10.1145/378239.379053 dblp:conf/dac/ZhouSN01 fatcat:h4544a4bvrcjdhp64epskxrh4a

Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis

Tong Xiao, Malgorzata Marek-Sadowska
2002 VLSI design (Print)  
Crosstalk-induced delay in deep sub-micron digital circuits can be quite significant and difficult to determine because of dependency on neighboring signals.  ...  In this paper we study the problem of incorporating temporal and functional information to improve the accuracy of crosstalk aware static timing analysis.  ...  This work was supported in part by the National Science Foundation grant CCR 9811528, and by the State of California MICRO grant through Conexant and Synopsys.  ... 
doi:10.1080/1065514021000012264 fatcat:7b2h3ibfy5dk5nybbdxdshvmja

Functional correlation analysis in crosstalk induced critical paths identification

Tong Xiao, Malgorzata Marek-Sadowska
2001 Proceedings of the 38th conference on Design automation - DAC '01  
In deep submicron digital circuits capacitive couplings make delay of a switching signal highly dependent on its neighbors' switching times and switching directions.  ...  Ignoring the mutual relationship among the signals may result in a very pessimistic estimation of circuit delay.  ...  This may cause delays of switching signals to be highly dependent on switching times and switching directions of their coupled neighbors, and it may also create noise signals on coupled neighbors [11]  ... 
doi:10.1145/378239.379041 dblp:conf/dac/XiaoM01 fatcat:hkgvnjrx65fpxfzwvpyc4a3pmy

Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk

Chuan Lin, Hai Zhou
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we show that the tradeoff between a latch and a flop can be leveraged in a sequential circuit design with crosstalk, so that the clock period is minimized by selecting a configuration of  ...  Experiments on our heuristic algorithm for finding an optimal configuration of mixed latches and flops showed promising results.  ...  We choose to characterize d i by (4) instead of the more aggressive formulation with d i = max(a i , T − w p(i) ) in In the presence of crosstalk, however, switching windows at both memory elements and  ... 
doi:10.1109/tcad.2006.888273 fatcat:rbhcnsyaenevrb77ffgx6yjgp4

Static timing analysis for level-clocked circuits in the presence of crosstalk

S. Hassoun, C. Cromer, E. Calvillo-Gamez
2003 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
First, coupling in a sequential circuit can occur because of the proximity of a victim's switching input to any periodic occurrence of the aggressor's input switching window.  ...  This paper addresses static timing analysis in the presence of cross talk for circuits containing levelsensitive latches, typical in high-performance designs. The paper focuses on two problems.  ...  EXPERIMENTAL RESULTS Our experiments evaluate the effectiveness of our algorithm in verifying clock schedules in the presence of crosstalk.  ... 
doi:10.1109/tcad.2003.816209 fatcat:medcsh3rvvg3ramkv7tplnxhza

Statistical gate delay calculation with crosstalk alignment consideration

Andrew B. Kahng, Bao Liu, Xu Xu
2006 Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06  
This effect is as significant as multiple-input switching on gate delay variation [2].  ...  We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects.  ...  Compare the impact of gate length variation on gate delay in the presence of crosstalk effect with that in the absence of crosstalk effect.  ... 
doi:10.1145/1127908.1127961 dblp:conf/glvlsi/KahngLX06 fatcat:dkvyupcsxrcdplz6ltn5yqimhq

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation

Ravishankar Arunachalam, Ronald DeShawn Blanton, Lawrence T. Pileggi
2002 VLSI design (Print)  
The impact of this switching on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded.  ...  Our algorithm accounts for glitches on aggressors that can be caused by static and dynamic hazards in the circuit. Results on industrial examples and benchmark circuits show the value of our approach.  ...  This implies that to have an effect on delay, the window of the noise waveform at the victim fanout should overlap with the window of the victim output without noise.  ... 
doi:10.1080/1065514021000012228 fatcat:v5yneyqzfjbclokwi4bvy5ngvm

On switch factor based analysis of coupled RC interconnects

Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
2000 Proceedings of the 37th conference on Design automation - DAC '00  
Our main result is that 2C c (or, SF = 2), where C c is the static coupling capacitance, is not a correct upper bound when calculating interconnect delay in presence of crosstalk: we show that for signals  ...  Delay with SF = 3 can still be underestimating because of exponential waveforms. 2 This is based on heuristic charge-sharing analysis.  ...  " grounded capacitance that is used in delay and noise calculations. 2 Analysis of victim line delay in the presence of crosstalk from a neighboring aggressor line 3 assumes that switch factors range  ... 
doi:10.1145/337292.337318 dblp:conf/dac/KahngMS00 fatcat:b6fzxvahfbbubl47x2ppz5tiva
« Previous Showing results 1 — 15 out of 1,335 results