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On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation

Xiao Liu, Qiang Xu
2008 2008 17th Asian Test Symposium  
In this paper, we propose to reuse these precious TAM resources for real-time debug data transfer in post-silicon validation.  ...  One of the main difficulties in post-silicon validation is the limited debug access bandwidth to internal signals.  ...  ., Ltd. for his insightful comments to this work.  ... 
doi:10.1109/ats.2008.83 dblp:conf/ats/LiuX08 fatcat:kgpiuchbf5bf5dtmp5uolxacye

On signal tracing in post-silicon validation

Qiang Xu, Xiao Liu
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
It is increasingly difficult to guarantee the first silicon success for complex integrated circuit (IC) designs. Post-silicon validation has thus become an essential step in the IC design flow.  ...  Tracing internal signals during circuit's normal operation, being able to provide real-time visibility to the circuit under debug (CUD), is one of the most effective silicon debug techniques and has gained  ...  A widely-adopted post-silicon validation technique utilized by the industry is to reuse the IEEE Std. 1149.1 (JTAG) test access port and existing design for test (DfT) structures in the circuit (e.g.,  ... 
doi:10.1109/aspdac.2010.5419883 dblp:conf/aspdac/XuL10 fatcat:5ftlnjsgmbf6ro5vvlufbfvnhq

A Multi-Core Debug Platform for NoC-Based Systems

Shan Tang, Qiang Xu
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
As traditional debug architecture for busbased systems is not readily applicable to identify bugs in NoC-based systems, in this paper, we present a novel debug platform that supports concurrent debug access  ...  Network-on-Chip (NoC) is generally regarded as the most promis- ing solution for the future on-chip communication scheme in gigascale integrated circuits.  ...  Therefore, efficient and effective post-silicon validation techniques need to be developed to reduce time-to-market.  ... 
doi:10.1109/date.2007.364402 dblp:conf/date/TangX07 fatcat:jczs6phuprgsbbtntrfop73ss4

On-Chip Error Detection Reusing Built-in Self-Repair for Silicon Debug

Hayoung Lee, Hyunggoy Oh, Sungho Kang
2021 IEEE Access  
These studies reuse test architectures such as the scan chain, test access mechanisms, test bus, IEEE 1149.1, 1500 test wrapper, and/or caches.  ...  DRAM-BASED SILICON DEBUG The main concept of the DRAM-based method is to transfer the debug data from buffers to a larger on-chip DRAM.  ...  For more information, see https://creativecommons.org/licenses/by/4.0/ This article has been accepted for publication in a future issue of this journal, but has not been fully edited.  ... 
doi:10.1109/access.2021.3071517 fatcat:vf3pxetxu5avrpvoo6q3cfhkz4

Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks

Bart Vermeulen, Kees Goossens
2010 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)  
Post-silicon debugging of a system on chip (SOC) is complex due to (1) the intrinsic limits on the internal observability, (2) the absence of a single global clock, and (3) the need for asynchronous intellectual  ...  We merge the required on-chip hardware to support this debug functionality with the traditional debug architecture that reuses the manufacturing scan chains for debug.  ...  Manufacturing test scan chains are often reused to interactively debug silicon [8] - [10] .  ... 
doi:10.1109/hldvt.2010.5496668 dblp:conf/hldvt/VermeulenG10 fatcat:hkaj67cg2be4fo36vota2gy7pm

An infrastructure for debug using clusters of assertion-checkers

M.H. Neishaburi, Zeljko Zilic
2012 Microelectronics and reliability  
Once assertions are converted to hardware modules and incorporated into a debug infrastructure, the post-silicon debug can benefit from the additional observability provided by such assertions.  ...  Assertion Based Verification (ABV) is one of the instrumental pre-silicon verification techniques.  ...  Although post-silicon validation mechanisms can offer a raw performance in terms of the execution speed of test cases, they need to be improved in order to increase the real-time observability of the signals  ... 
doi:10.1016/j.microrel.2012.04.016 fatcat:stvih5wnirdgxhxnjz4soimelq

A reconfigurable design-for-debug infrastructure for SoCs

Miron Abramovici, Paul Bradley, Kumar Dwarakanath, Peter Levin, Gerard Memmi, Dave Miller
2006 Proceedings of the 43rd annual conference on Design automation - DAC '06  
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug.  ...  A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port.  ...  There is a huge difference between the variety and the sophistication of the tools available for pre-silicon verification and the lack of automation associated with post-silicon validation.  ... 
doi:10.1145/1146909.1146916 dblp:conf/dac/AbramoviciBDLMM06 fatcat:ojux2nb3wjfajnuu6bhp5pzfce

A reconfigurable design-for-debug infrastructure for SoCs

M. Abramovici, P. Bradley, K. Dwarakanath, P. Levin, G. Memmi, D. Miller
2006 Proceedings - Design Automation Conference  
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug.  ...  A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port.  ...  There is a huge difference between the variety and the sophistication of the tools available for pre-silicon verification and the lack of automation associated with post-silicon validation.  ... 
doi:10.1109/dac.2006.238683 fatcat:3fl4qqsutjd3te6jleaw5o6wgu

Post-silicon platform for the functional diagnosis and debug of networks-on-chip

Rawan Abdel-Khalek, Valeria Bertacco
2014 ACM Transactions on Embedded Computing Systems  
Each node's local cache is configured to temporarily store the snapshot logs in a designated area reserved for post-silicon validation and relinquished after product release.  ...  To support this goal, an increasing fraction of the validation effort has shifted to post-silicon validation, because it permits exercising network activities that are too complex to be validated in pre-silicon  ...  Post-silicon validation for networks-on-chip.  ... 
doi:10.1145/2567936 fatcat:danvptshjnfrzen6f5rblc3cta

SoC Security Properties and Rules [article]

Nusrat Farzana, Farimah Farahmandi, Mark M. Tehranipoor
2021 IACR Cryptology ePrint Archive  
A system-on-chip (SoC) security can be weakened by exploiting the potential vulnerabilities of the intellectual property (IP) cores used to implement the design and interaction among the IPs.  ...  In this paper, we develop 'SoC Security Property/Rule Database' and make it available publicly to all researchers to facilitate and extend security verification effort to address this need.  ...  Moreover, the synthesizable properties are placed on silicon as a monitor for specific events at the run-time or provide closures for post-silicon validation [12] .  ... 
dblp:journals/iacr/FarzanaFT21 fatcat:ngtr63o5vbddnnx6ioyerguqwm

High Quality System Level Test and Diagnosis

Artur Jutman, Matteo Sonza Reorda, Hans-Joachim Wunderlich
2014 2014 IEEE 23rd Asian Test Symposium  
The reuse for system test of design for test structures and test data developed at chip level is discussed, including the limitations and research challenges.  ...  Structural test methods have to be complemented by functional test methods. State-of-the-art and leading edge research for functional testing will be covered.  ...  In addition, there may be no special media for the test data transfer and existing buses have to be reused.  ... 
doi:10.1109/ats.2014.62 dblp:conf/ats/JutmanRW14 fatcat:mfbixngx3fds5imeookrnx3mfi

Interconnection fabric design for tracing signals in post-silicon validation

Xiao Liu, Qiang Xu
2009 Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09  
Post-silicon validation has become an essential step in the design flow of today's complex integrated circuits.  ...  These trace signals need to be transferred to on-chip buffers and/or off-chip trace ports for analysis.  ...  ACKNOWLEDGEMENTS This work was supported in part by the General Research Fund CUHK417406, CUHK417807, and CUHK418708 from Hong Kong SAR Research Grants Council, and in part by a grant N_CUHK417/08 from  ... 
doi:10.1145/1629911.1630006 dblp:conf/dac/LiuX09 fatcat:quzfhmwwqrhbvmj7xuykgoib34

Using a soft core in a SoC design: experiences with picoJava

S. Dey, D. Panigrahi, Li Chen, C.N. Taylor, K. Sekar, P. Sanchez
2000 IEEE Design & Test of Computers  
Acknowledgments We would like to thank Sun Microsystems for open licensing of the picoJava core, and the sponsors of the SRC Cu-Design Contest for access to the 0.18um Cu technology.  ...  We would like to thank Ying Chen for his help with the picoJava synthesis process, Dong-Gi Lee for his help in generating the memory components, and Yi Zhao and Xiaoliang Bai for helping with the physical  ...  We describe our experience in validating the RTL model, as well as a methodology we have developed for validating the post-synthesis gate-level model.  ... 
doi:10.1109/54.867896 fatcat:x52yvcjg4jbwvc3szbbrouowcm

Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System Characterization of the Multi-Gigahertz Interfaces on the Cell Processor

P. Yeung, A. Torres, P. Batra
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
Design-for-test (DFT) techniques are continuously used in designs to help identify defects during silicon manufacturing.  ...  In this paper, we shall discuss the test infrastructure and methodologies used to accelerate bring-up and in-system silicon characterization for high-speed mixed-signal I/O.  ...  Acknowledgements We extend our thanks and gratitude to Wai-Yeung Yip, David Nguyen, Kenyon Han, Melissa Frank, Paula Tostado and Keisuke Saito of Rambus Inc. for reviewing the paper. References  ... 
doi:10.1109/date.2007.364681 dblp:conf/date/YeungTB07 fatcat:oe3qm36zxjf5vmnv5y3az25rfu

HardFails: Insights into Software-Exploitable Hardware Bugs

Ghada Dessouky, David Gens, Patrick Haney, Garrett Persyn, Arun K. Kanuparthi, Hareesh Khattri, Jason M. Fung, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
2019 USENIX Security Symposium  
RISC-V SoCs.  ...  We envision our RISC-V testbed of RTL bugs providing a rich exploratory ground for future research in hardware security verification and contributing to the open-source hardware landscape.  ...  Acknowledgments We thank our anonymous reviewers and shepherd, Stephen Checkoway, for their valuable feedback.  ... 
dblp:conf/uss/DessoukyGHPKKFS19 fatcat:nffg6ywb2jgidday7dp5g6sn4y
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