Filters








9,835 Hits in 7.4 sec

3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs

Yibo Chen, Guangyu Sun, Qiaosha Zou, Yuan Xie
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
This paper proposes an incremental system-level synthesis framework that tightly integrates behavioral synthesis of modules into the layer assignment and floorplan ning stage of 3D IC design.  ...  Physical planning of three dimensional integrated circuits is substantially different from that of traditional planar integrated circuits, due to the presence of multiple layers of dies.  ...  Krishnan et. al [7] proposed a 3D layout aware binding algorithm for high-level synthesis of 3D ICs.  ... 
doi:10.1109/date.2012.6176673 dblp:conf/date/ChenSZX12 fatcat:obdpcxcyezdjlg3kd45s77dcze

Table of contents

2021 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
3D Design & OptimizationOptimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs ...Design Automation for Cyber Physical Systems and Internet  ...  Systems on Multicore Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ... 
doi:10.1109/tcad.2021.3108338 fatcat:ejmvzriq3nfvpc3lj4s43ietoe

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling [article]

Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric
2020 arXiv   pre-print
3D integration, i.e., stacking of integrated circuit layers using parallel or sequential processing is gaining rapid industry adoption with the slowdown of Moore's law scaling. 3D stacking promises potential  ...  In this talk, we will discuss some key challenges associated with 3D design and how design-for-3D will require us to break traditional silos of micro-architecture, circuit/physical design and manufacturing  ...  this new paradigm. 3D integration is a wide term encompassing technologies that enable vertical integration of more than one layer of active transistors and interconnects with the goal of increasing compute  ... 
arXiv:2005.10866v1 fatcat:3o32jrvjsjamffta4le7p4hxwi

Improved result of TSV and Slew aware 3D Gated Clock Tree Synthesis using charge recycling configuration

R. Rajalakshmi, S. M. Ramesh, P. Sivakumar
2021 3C Tecnología  
In physical design of Integrated Circuits (ICs) especially after placement, Clock Tree Synthesis (CTS) plays a major part in the general chip efficiency.  ...  Three Dimensional Integrated Circuits (3D ICs) based on Through Silicon Via (TSV) present a major challenge for IC developers. 3D gated CTS on the TSV-TSV coupling model is an effective approach to reduce  ...  IMPORTANCE OF CTS IN 3D ICS In this section, the importance of clock tree synthesis, the effect of TSV on 3D integrated circuits and skew reduction are first discussed and then power gating logic is inserted  ... 
doi:10.17993/3ctecno.2021.specialissue8.667-687 fatcat:glsqssoi3rcqfhryj73jonrwrq

Physical Design Automation for 3D Chip Stacks

Johann Knechtel, Jens Lienig
2016 Proceedings of the 2016 on International Symposium on Physical Design - ISPD '16  
We survey major design challenges for 3D chip stacks with particular focus on their implications for physical design.  ...  The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality  ...  They applied automated synthesis of RTL modules and physical-design prototyping using feedback loops. More recently, Martin et al.  ... 
doi:10.1145/2872334.2872335 dblp:conf/ispd/KnechtelL16 fatcat:3kigpmhpnjahbow2yptm2cjrzm

Design of Application-Specific 3D Networks-on-Chip Architectures [chapter]

Shan Yan, Bill Lin
2010 Integrated Circuits and Systems  
The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip design innovations, including the prospect of extending emerging Systems-on-Chip  ...  We present novel 3D-NoC synthesis algorithms that make use of accurate power and delay models for 3D wiring with through-silicon vias.  ...  Three dimensional interconnect provides a flexible way to integrate these disparate technologies into a single systems-on-chip (SoC) design.  ... 
doi:10.1007/978-1-4419-7618-5_8 dblp:series/icas/YanL11 fatcat:5pe4dm27snfyvh72v76kqj2s4e

Three-dimensional multiprocessor system-on-chip thermal optimization

Chong Sun, Li Shang, Robert P. Dick
2007 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '07  
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency.  ...  Performance evaluation on a set of multiprogrammed and multithreaded benchmarks indicates that the proposed techniques can optimize 3D MPSoC power consumption, power profile, and chip peak temperature.  ...  Xie and Hung propose a thermal-aware task allocation and scheduling algorithm to minimize IC peak temperature [23] . Thermal optimization of 3D ICs has focused on physical design.  ... 
doi:10.1145/1289816.1289846 dblp:conf/codes/SunSD07 fatcat:qvj5wcqnojcsplgec4iizmx7re

Design of application-specific 3D Networks-on-Chip architectures

Shan Yan, Bill Lin
2008 2008 IEEE International Conference on Computer Design  
The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip design innovations, including the prospect of extending emerging Systems-on-Chip  ...  We present novel 3D-NoC synthesis algorithms that make use of accurate power and delay models for 3D wiring with through-silicon vias.  ...  Three dimensional interconnect provides a flexible way to integrate these disparate technologies into a single systems-on-chip (SoC) design.  ... 
doi:10.1109/iccd.2008.4751853 dblp:conf/iccd/YanL08 fatcat:pp525sypzjbu7fp4df6kc4cyfq

Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs

Meng-Ling Tsai, Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
Integrating Multi-Processor System-on-Chips (MP-SoCs) with 3D-stacked reconfigurable SRAM tiles has been proposed for embedded systems with high memory demands.  ...  The goal of the proposed algorithm is to optimize the performance of the memory system by minimizing the on-chip memory access latency, the number of off-chip memory accesses, and the number of reconfigurations  ...  We thank Professor Takeshi Tokuyama from Graduate School of Information Sciences, Tohoku University, for his valuable comments and suggestions.  ... 
doi:10.7873/date.2014.336 dblp:conf/date/TsaiCCC14 fatcat:nfatldbfdjci5iv7lsvcrr3bj4

Guest Editors' Introduction: Opportunities and Challenges of 3D Integration

David S. Kung, Yuan Xie
2009 IEEE Design & Test of Computers  
His research interests include logic and physical synthesis, and design methodology for high-performance microprocessors.  ...  However, the fate of 3D integration will ultimately depend on whether or not there are profitable and widespread applications that can reap the benefits of 3D integration and whether or not the return  ... 
doi:10.1109/mdt.2009.115 fatcat:ls726mpgmbho7fgwzmjmk23qze

Chemical-mechanical polishing aware application-specific 3D NoC design

Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan
2011 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
Experimental results show that our CMP-aware 3D NoC design can achieves lower TSV height variation, higher performance and lower power consumption than the previous state-of-the-art 3D NoC designs.  ...  In this paper, we propose the first chemical-mechanical polishing (CMP) aware application-specific three-dimensional (3D) network-on-chip (NoC) design that minimizes through-silicon-via (TSV) height variation  ...  Our vertical integration managing architecture, physical design, and manufacturing issues together enables a reliable and robust 3D NoC with low power consumption and high performance.  ... 
doi:10.1109/iccad.2011.6105327 dblp:conf/iccad/JangHYP11 fatcat:sfrtgzmpevbaxfxh4dobzg3bw4

Chemical-Mechanical Polishing-Aware Application-Specific 3D NoC Design

Wooyoung Jang, D. Z. Pan
2013 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Three-dimensional (3D) integration with throughsilicon vias (TSVs) is promising in the integration of many cores into a single chip.  ...  the previous state-of-the-art 3D NoC designs.  ...  Our vertical integration managing architecture, physical design, and manufacturing issues together enabled a reliable and robust 3D NoC.  ... 
doi:10.1109/tcad.2013.2237771 fatcat:ewkfutvv6nhhlgg2n3uiobnld4

Clock tree embedding for 3D ICs

Tak-Yung Kim, Taewhan Kim
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
of the total wirelength  Clock Tree Synthesis Flow for 3D ICs  Experimental Results  Conclusions 1 3-Dimensional Integrated Circuit  Chip with multiple layers of active devices  by vertically stacking  ...  /Power/Area benefit  Small form factor  System size reduction  Heterogeneous technology integration  Manufacturing cost  Yield  Thermal problem  Noise problem  Physical design automation 3D Physical  ...  DME on 3D Design Space  Construction of merging segment ms(v), with TRR (Tilted Rectangular Region)  Edge length |e x | calculation is modified to consider the delays of TSVs as well as 2D wires.  The  ... 
doi:10.1109/aspdac.2010.5419833 dblp:conf/aspdac/KimK10 fatcat:rkgr42ch5rhhzj266fzxhqk5gy

3D Stacked Cache Data Management for Energy Minimization of 3D Chip Multiprocessor

K. Suresh Kumar, S. Anitha, M. Gayathri
2015 International Journal of Students Research in Technology & Management  
New tendencies envisage 3D Multi-Processor System-On-Chip (MPSoC) design as a promising solution to keep increasing the performance of the next-generation high performance computing (HPC) systems.  ...  However, as the power density of HPC systems increases with the arrival of 3D MPSoCs with energy reduction achieving up to 19.55% by supplying electrical power to the computing equipment and constantly  ...  There are prior works on the temperature aware management for 3D CMP.  ... 
doi:10.18510/ijsrtm.2015.325 fatcat:wxb36ypu2zfizmltie2xjqvxe4

Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video

Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang, Wei Hwang
2014 2014 27th IEEE International System-on-Chip Conference (SOCC)  
In this paper, a thermal-aware hierarchal memory management unit (MMU) in a 3D-Stacked DRAM model is proposed for 3D HD video systems.  ...  Moreover, power reduction of up to 43.46% can be realized in low power mode by the dynamic thermal-aware refresh timing control and deep power down detection. I.  ...  For the requirements of large physical memory space and high memory bandwidth in real-time 3D video systems, a thermal-aware hierarchal memory management unit (MMU) is proposed with a 3D-Stacked DRAM model  ... 
doi:10.1109/socc.2014.6948903 dblp:conf/socc/ChangHCCH14 fatcat:usgl5fe2obcdrdyv447pdssl5e
« Previous Showing results 1 — 15 out of 9,835 results