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Lecture Notes in Computer Science
Our approach is inspired by work in the related area of evaluating monotone Boolean circuits [11, 9, 15, 3, 17, 5] . ... Can we improve over the sequential approach by evaluating entire blocks of path positions in parallel? In this paper, we show that LTL path checking can indeed be parallelized efficiently. ... Note that an EV circuit with all variables on the outer face is OIF. The evaluation of full OIF circuits can be parallelized efficiently. ...doi:10.1007/978-3-642-02930-1_20 fatcat:atoqrzx5bjea3o3pe2svjfjv4a
Nonetheless, it is found that for some ensembles of random circuits, saturation to a fixed truth value occurs rapidly so that evaluation of the circuit can be accomplished in much less parallel time than ... of the circuit. ... of parallel evaluation of the circuit. ...doi:10.1088/1742-5468/2011/04/p04015 fatcat:n5i6jde64rc6lmnnglvlbi6voe
The results of the student's HOTS on the analysis provided by students from excellence classes are 71.25% indicating high category and regular class 48.71% indicating medium category. ... The number of samples involved 59 students consisting of 30 students from the excellence class and 29 students from the regular class. ... 2, 3 Electrical power 4 2 C5 (Evaluate) Ohm's law 5 Barriers replacement series and parallel 6, 7 Current-voltage in series and parallel circuits 8 The data obtained and analyzed using descriptive statistics ...doi:10.21009/1.05211 fatcat:jlqal4zcsncmvh4a5yc7ungqyi
We prove that for linear-time temporal logic (LTL), path checking can be efficiently parallelized. ... In addition to the core logic, we consider the extensions of LTL with bounded-future (BLTL) and past-time (LTL+Past) operators. ... Note that an evaluated planar circuit with all variable gates on the outer face is one-input-face. The evaluation of one-input-face planar circuits can be parallelized efficiently. ...doi:10.2168/lmcs-8(4:10)2012 fatcat:eabc7iq4mvhwlfky7byt4xcdji
The evaluation of monotone planar circuits is shown to be in NC, in fact in LOGCFL. ... The equivalence of complexity classes defined by sequential space and uniform aggregate hardware is established. ... ACKNOWLEDGMENTS We thank Allan Borodin, Les Goldschlager, Jia-wei Hong, Nicholas Pippenger, Charles Rackoff, Walter Ruzzo, and Martin Tompa for valuable discussions about parallel computation, and an anonymous ...doi:10.1016/0890-5401(89)90009-6 fatcat:tiflzvrbpnfahnus3mnsncprzq
We present connections to space-bounded classes, simulation of parallel computational models such as vector machines, and a discussion of the charac- terizations of various nonuniform classes in terms ... Also parallel classes defined by bounded fan-in circuits can be characterized in such a way, and thus a positive solution to C. B. Wilson’s [SIAM J. ...
As a consequence, algorithms for automated analysis of finite state systems based on bisimulation seem to be inherently sequential in the following sense: the design of an NC algorithm to solve any of ... In finite labelled transition systems the problems of deciding strong bisimilarity, observation equivalence and observation congruence are P-complete under many-one NC -reducibility. ... For the formal study of the possible existence of parallel algorithms we will consider two complexity classes: P and N C. ...doi:10.1007/bf03180566 fatcat:5aleljx7hnbmxb6fxikwiqg47i
equal to special evaluations of the Tutte polynomial (e.g., the total number of circuit-cocircuit reversal classes equals t(M;1,1), the number of bases of the matroid). ... By relating these classes to activity classes studied by the first author and Las Vergnas, we give an alternative proof of the above results and a proof of the converse statements that these equalities ... The role of the first author of this paper has been to simplify and extend a preprint written at the initiative of the second author. ...arXiv:1707.00342v2 fatcat:qw3vnfx325gmxf5lepfzn57wqi
Summary: “We treat the problem of parallel evaluation of two important classes of circuits: polynomial degree circuits and leveled monotone planar circuits. ... Rao (1-JHOP-D) On the parallel evaluation of classes of circuits. Foundations of software technology and theoretical computer science (Bangalore, 1990), 232-237, Lecture Notes in Comput. ...
We observe that the few-shot learned embeddings generalize to unseen classes and suffer less from the circuit bypass problem compared with other approaches. ... Quantum embedding learning is an important step in the application of quantum machine learning to classical data. ... Department of Energy, Office of Science, under contract number DE-AC02-06CH11357. We thank William Tang for the helpful discussions. VIII. ...arXiv:2204.04550v1 fatcat:otncnu5bqndkfn2cy7n4bmyz2u
Using a proofs-as-programs correspondence, Terui was able to compare two models of parallel computation: Boolean circuits and proof nets for multiplicative linear logic. ... We can then encode constant-depth circuits and compare complexity classes below logspace, which were out of reach with the previous translations. ... Boolean circuits Boolean circuits (definition 2) are of great interest in the study of complexity, for instance because of the efficiency of their parallel evaluation. ...doi:10.4204/eptcs.75.2 fatcat:mxdz7yxowbdmdndsso35kfseyq
In particular, the diagram data structure allows to encode various kinds of quantum processes, with functors for classical simulation and optimisation, as well as compilation and evaluation on quantum ... This includes the ZX calculus and its many variants, the parameterised circuits used in quantum machine learning, but also linear optical quantum computing. ... On the one hand, PyZX  performs quantum circuit optimisation via automated rewriting of ZX-diagrams. ...arXiv:2205.05190v1 fatcat:izzrcumgl5dtxpumwfgudna6dm
Lecture Notes in Computer Science
Canonical circuits are optimal with respect to maximal and as-early-as-possible parallelism of targets within gates. ... As the main result, we show that shift-reduced circuits are unique canonical representatives of their shift equivalence classes. ... The shifting defines an equivalence relation on circuits. Each equivalence class contains only circuits that are semantically equivalent. ...doi:10.1007/978-3-319-30000-9_46 fatcat:hbdroihlxffojo55asekn4noka
These algorithms use as a model of parallel machine a family of circuits with polynomial size and polylogarithmic depth, for which a logspace uniformity condition is valid. ... On the other hand, for a wide variety of problems, fast parallel algorithms have been designed during the last years. ... ACKNOWLEDGMENT Thanks are due to Ricard Gavalda for helpful discussions as well as for a careful reading of the manuscript. ...doi:10.1016/0885-064x(92)90008-y fatcat:wiszsifprvfoveov6ykx5ukvla
The method combines the population-of-solutions ideas from evolutionary algorithms with a novel variant of pattern search, and supports transparent network parallelism. ... Analog synthesis tools have traditionally traded quality for speed, substituting simplified circuit evaluation methods for full simulation in order to accelerate the numerical search for solution candidates ... The code for each parallel node begins on line 1 of Fig. 7 . We start with a population of circuit solutions, sorted on cost. ...doi:10.1109/43.848091 fatcat:pg6ivtmrorbzxgwqlt4fgowahi
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