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Diametrical Mesh Of Tree (D2D-MoT) Architecture: A Novel Routing Solution For NoC [article]

Prasun Ghosal, Sankar Karmakar
2012 arXiv   pre-print
In this paper, we present a Mesh routing architecture, which is called Diametrical 2D Mesh of Tree, based on Mesh-of-Tree (MoT) routing and Diametrical 2D Mesh.  ...  Network-on-chip (NoC) is a new aspect for designing of future System-On-Chips (SoC) where a vast number of IP cores are connected through interconnection network.  ...  The network is used for packet switched on-chip communication among cores [2] [3] [4] [5] [6] [7] . B.  ... 
arXiv:1212.2874v1 fatcat:gjymqbwcrjcdzeyz3apqsjhy7u

A spanning bus connected hypercube: a new scalable optical interconnection network for multiprocessors and massively parallel systems

A. Louri, C. Neocleous
1997 Journal of Lightwave Technology  
The SBCH uses the hypercube topology as a basic building block and connects such building blocks using multidimensional spanning buses.  ...  An optical implementation methodology is proposed for SBCH. The implementation methodology combines both the advantages of free space optics with those of wavelength division multiplexing techniques.  ...  In 1996, he was the recipient of the Japanese Society for the Promotion of Science Fellowship.  ... 
doi:10.1109/50.596971 fatcat:ohpyom626rdyzdsjgoemm5qtcu

pp-mess-sim: a flexible and extensible simulator for evaluating multicomputer networks

J. Rexford, Wu-Chang Feng, J. Dolter, K.G. Shin
1997 IEEE Transactions on Parallel and Distributed Systems  
, traffic patterns, and performance metrics with collections of packets, instead of the underlying router model.  ...  Sample simulation experiments capitalize on this flexibility to compare network architectures under various application workloads.  ...  Fig. 10 shows the performance of various switching schemes using static dimension-ordered routing on an 8 × 8 square mesh; each node independently generates 16-word packets with exponentially-distributed  ... 
doi:10.1109/71.569653 fatcat:u47by6qsbbhbnbfa2vs7xd5agy

Configurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC

Arash Farhadi Beldachi, Mohammad Hosseinabady, Jose Luis Nunez-Yanez
2013 International Journal of Reconfigurable and Embedded Systems (IJRES)  
Overall, the mesh network with a four local ports router offers a higher level of performance with lower complexity compared to the traditional mesh with one local port router.  ...  The configurable router uses distributed routing suitable for regular topologies and can vary the number of local ports and communication ports to build multi dimensional networks (i.e., 2D and 3D) with  ...  ReCoBus [10] introduced a technique to generate On-Chip buses suitable for dynamic partially reconfigurable platforms.  ... 
doi:10.11591/ijres.v2.i1.pp27-48 fatcat:n7ovzjxtyrff5htmvzuxsjifni

Hardware for multiconnected networks: the design flow

G Campobello
2004 Information Sciences  
Such performance is not absolute, in fact, an efficient network for one definite application may be inefficient for another [1] .  ...  This is characterized by three elements: the topology, the routing algorithm and the policy of flow control.  ...  Generally, for multidimensional networks that are symmetrical to each dimension such as Hypercubes, Mesh, k-ary n-cube and Recursive-Cube of Ring (RCR), the mean distance is half of the maximum distance  ... 
doi:10.1016/j.ins.2003.09.001 fatcat:q3qndfea2vdpfkqfkgxnlfbxpm

Randomized Routing and Sorting on Fixed-Connection Networks

F.T. Leighton, B.M. Maggs, A.G. Ranade, S.B. Rao
1994 Journal of Algorithms  
This strategy yields randomized algorithms for routing and sorting in time proportional to the diameter for meshes, butter ies, shu e-exchange graphs, multidimensional arrays, and hypercubes.  ...  Its basis is a randomized on-line algorithm for scheduling any set of N packets whose paths have congestion c on any bounded-degree leveled network with depth L in O(c + L + logN) steps, using constant-size  ...  Let T be the time at which the last packet arrives. Then Pr T ( 2 + 1)L + w] Pr T ( 2 + 1)L + wjc < (L + w)= 3 4 ] + Pr c (L + w)= 3 4 ]: We use Lemma 8.6 to bound the rst term on the right.  ... 
doi:10.1006/jagm.1994.1030 fatcat:6pjcbmlvvjbcpguivqcrenvfqa

Expandable Networks for Neuromorphic Chips

Paul A. Merolla, John V. Arthur, Bertram E. Shi, Kwabena A. Boahen
2007 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
For each event, the axon's identity is encoded with a unique binary word, an address event.  ...  This design, which is integrated on each chip, connects neurons at corresponding locations on each of the chips (pointwise connectivity) and supports oblivious, targeted, and excluded delivery of spikes  ...  This controller 4 Our expandability argument also pertains to multidimensional grids and buses.  ... 
doi:10.1109/tcsi.2006.887474 fatcat:cn5sbtz5abcxzf7r4od54t7bpa

A survey of research and practices of Network-on-chip

Tobias Bjerregaard, Shankar Mahadevan
2006 ACM Computing Surveys  
This has triggered work on skew tolerant circuit design [Nedovic et al. 2003], which deals with clockskew by relaxing the need for timing margins, and on the use of optical waveguides for on-chip clock  ...  Shrinking metal pitches, in order to maintain sufficient routing densities, is appropriate at the local level where wire lengths also decrease with scaling.  ...  Also our grateful thanks to professor Axel Jantsch (KTH -Stockholm, Sweden) and Andrei Radulescu (Phillips -Eindhoven, Netherlands) for their valuable review of the survey as it was closing in on its final  ... 
doi:10.1145/1132952.1132953 fatcat:kpaihucc7rbqfg2ujtg7xubbqq

The Scalable Coherent Interface (SCI)

D.B. Gustavson, Qiang Li
1996 IEEE Communications Magazine  
access t o distributed data, and so on.  ...  There is rapidly increasing demand for very-high-performance networked communication for workstation clusters, distributed databases, multiprocessors, industrial data acquisition and control systems, shared  ...  various dimensions of a multidimensional mesh.  ... 
doi:10.1109/35.533919 fatcat:icmnbvnsfffv7hzxejen5fd77m

On-Chip Interconnection Architecture of the Tile Processor

D. Wentzlaff, P. Griffin, H. Hoffmann, Liewei Bao, B. Edwards, C. Ramey, M. Mattina, Chyi-Chang Miao, J.F. Brown, A. Agarwal
2007 IEEE Micro  
Acknowledgments We thank everyone on the Tilera team for their effort in designing the Tilera chip and accompanying software tools. iMesh, iLib, Multicore Hardwall, TILE64 and Tile Processor are trademarks  ...  The latency of each hop through the network is one cycle when packets are going straight, and one extra cycle for route calculation when a packet must make a turn at a switch.  ...  Instead of using buses or rings to connect the many on-chip cores, the Tile Architecture couples its processors using five 2D mesh networks, which provide the transport medium for off-chip memory access  ... 
doi:10.1109/mm.2007.4378780 fatcat:mij2pf6ctvbzzimbyq5i2p52d4

End-to-end delays in polling tree networks

P. Beekhuizen, T.J.J. Denteneer, J.A.C. Resing
2008 Proceedings of the 3rd International Conference on Performance Evaluation Methodologies and Tools  
We obtain an exact expression for the overall mean end-to-end delay, and an approximation for the mean end-to-end delay of packets per source.  ...  The study is motivated by Networks on Chips where multiple processors share a single memory.  ...  Furthermore, it is mentioned that the class of MTBPs is one of the exceptional classes of multidimensional Markov chains for which the equilibrium distribution can be determined.  ... 
doi:10.4108/icst.valuetools2008.4248 dblp:conf/valuetools/BeekhuizenDR08 fatcat:wchbkbqwdfbjtk6szmciqls5qi

Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors

Nikita Nikitin, Javier de San Pedro, Jordi Cortadella
2013 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Based on this observation, a novel scalable analytical method is proposed to estimate the performance of highly parallel CMPs (hundreds or thousands of cores) with hierarchical interconnect networks.  ...  Moreover, faster analytical models are preferred to costly simulations for estimating the performance and power of CMP architectures.  ...  Ogras for insightful comments and helpful discussions.  ... 
doi:10.1109/tcad.2013.2272539 fatcat:gvj6nwhgjje7fpaarfimg37mf4

Analytical Performance Modeling of Hierarchical Interconnect Fabrics

Nikita Nikitin, Javier de_San Pedro, Josep Carmona, Jordi Cortadella
2012 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip  
This paper proposes a scalable analytical method to estimate the performance of highly parallel CMPs (hundreds of cores) with hierarchical interconnect fabrics.  ...  However, performance is highly determined by the latency of the memory subsystem, which in turn has a cyclic dependency with the memory traffic generated by the cores.  ...  This delay represents the latency of the on-chip network traversal and is defined using the routing function R : f → π(f ), that for any flow f returns its routing path π(f ).  ... 
doi:10.1109/nocs.2012.20 dblp:conf/nocs/NikitinPCC12 fatcat:l77hcjtg4bbjnlbewyv5krxp4u

Overview of the Blue Gene/L system architecture

A. Gara, M. A. Blumrich, D. Chen, G. L.-T. Chiu, P. Coteus, M. E. Giampapa, R. A. Haring, P. Heidelberger, D. Hoenicke, G. V. Kopcsay, T. A. Liebsch, M. Ohmacht (+3 others)
2005 IBM Journal of Research and Development  
It is designed to scale to 65,536 dual-processor nodes, with a peak performance of 360 teraflops.  ...  The Blue Genet/L computer is a massively parallel supercomputer based on IBM system-on-a-chip technology.  ...  Acknowledgment The Blue Gene/L project has been supported and partially funded by the Lawrence Livermore National Laboratory on behalf of the United States Department of Energy under Lawrence Livermore  ... 
doi:10.1147/rd.492.0195 fatcat:fod4gj7pbfgdxnd7nsxgfy4ini

High Fidelity Simulation of Network Nodes with RF-Ranging Capabilities

Hamed BASTANI, Andreas BIRK
2009 Sensors & Transducers  
Through experiments with real world devices and their simulation also in Matlab, the fidelity of the simulated models is shown.  ...  We first investigate practical response of the introduced wireless sensors and then present high fidelity simulation of a promising RF-based ranging technology based on real world sampled data.  ...  Packet Loss An analysis of the number of valid packets shows that the packet loss rate is increasing with respect to the distance increment.  ... 
doaj:9a58d9f521784bdfaf52c46c7eac199b fatcat:gffc7zquuzdnfb2o2skygvhite
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