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Technical visualizations in VLSI design

Phillip J. Restle
2001 Proceedings of the 38th conference on Design automation - DAC '01  
Visualization techniques were applied to several different types of VLSI design and simulation data. A number of different visualizations have been tried, with varying results.  ...  Examples include 3D visualization of voltage and currents from fullwave interconnect analysis, on-chip clock distribution networks, chip/package power supply noise analysis, wire congestion, chip layout  ...  In this case the Y-axis is exaggerated since this layout is actually 70 times as long as it is wide.  ... 
doi:10.1145/378239.378569 dblp:conf/dac/Restle01 fatcat:ybvkgfaflbfatfwkrj2shd5i3q

Replacing design rules in the VLSI design cycle

Paul Hurley, Krzysztof Kryszczuk, Mark E. Mason
2012 Design for Manufacturability through Design-Process Integration VI  
We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs.  ...  For one sample test site, and for the ORC Line Width error type ORC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.  ...  We obtained a sample of the Line Width error examples from an enumerated synthetic layout.  ... 
doi:10.1117/12.916428 fatcat:ynlfvefbkndcdmsiw5vwxx3o7q

Page 21 of Hewlett-Packard Journal Vol. 36, Issue 6 [page]

1985 Hewlett-Packard Journal  
But since a 132- hammer line printer requires as many output taps, a VLSI component would immediately encounter a costly packag- ing problem.  ...  This shift register is 2772 bits long, one storage cell for every dot that can be placed across a print row.  ... 

Crosstalk Minimization for Coupled RLC Interconnects Using Bidirectional Buffer and Shield Insertion

Damanpreet Kaur, Sulochana V
2013 International Journal of VLSI Design & Communication Systems  
With the help of these techniques crosstalk noise is controlled to a great extent in long interconnects.  ...  Crosstalk noise is often induced in long interconnects running parallel to each other.  ...  ACKNOWLEDGEMENTS We would like to extend a special thanks to C-DAC Mohali for providing us means to carry out our research work in meticulous way.  ... 
doi:10.5121/vlsic.2013.4304 fatcat:hshlsoed6zc6xhznsxgajbzm2m

Real Concern to High Speed VLSI Design for Interconnect Scaling

B Karthik
In this paper we show the effects of the classical scaling on the effective delay and the coupling capacitance.  ...  lines due to ever shrinking separation is also increasing to a noticeable level.  ...  equation ( 3 ) have a linear dependence on line length.  ... 
doi:10.26782/jmcms.spl.2019.08.00055 fatcat:4pwfppafb5h2tlib4rfmbtcj44

Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay

I. Koren, Z. Koren, D.K. Pradhan
1988 IEEE Journal of Solid-State Circuits  
Any change in the layout of a bus may affect the propagation delay of the bus and, as a consequence, the performance of the VLSI chip.  ...  Although this assumption may be valid in many cases, the cost-effectiveness of this proposed "robust" bus layout is questionable especially in the case of wide buses (e.g., 32 bit wide).  ...  Note that the above general description includes as special cases many alternative layouts.  ... 
doi:10.1109/4.330 fatcat:wen6kjtibrej3agbdt5c6ewk7m

Keynote address

2010 2010 International Conference on Recent Trends in Information, Telecommunication and Computing  
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines.  ...  Transistor performance depends heavily on gate and other dimensions. A 10% transistor gate variation can translate to as much as a variation of -15% to +25% in gate delay.  ...  The clock signal has already been brought into the multi-gigahertz range where inductance and other transmission line effects of on-chip long lines become important.  ... 
doi:10.1109/itc.2010.6 fatcat:kkuqcrh7hvgl7bd5uo7c7ysthm

The design of delay insensitive asynchronous 16-bit microprocessor

Byung-Soo Choi, Dong-Wook Lee, Dong-Ik Lee
1999 Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)  
In recent, asynchronous design has been resurged to exploit potential advantages of asynchronous VLSI such as; high-performance, low power consumption, timing fault tolerance and design cost reduction.  ...  To achieve our main purpose simple architecture and a pessimistic delay assumption has been selected. DINAMIK has been fabricated as a SOG using 0.6 technology.  ...  power consumption, since clock driving power increases in proportion to the area of a chip.  ... 
doi:10.1109/aspdac.1999.759703 dblp:conf/aspdac/ChoiLL99 fatcat:ycpyrl37bfhc5gtmhdyppqmguu

Architecting Microprocessor Components in 3D Design Space

Balaji Vaidyanathan, Wei-lun Hung, Feng Wang, Yuan Xie, Vijaykrishnan Narayanan, Mary Irwin
2007 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)  
An IPC improvement of 11% shown for a microprocessor implemented in 2-strata 3D technology. 20th International Conference on VLSI Design (VLSID'07) 0-7695-2762-0/07 $20.00  ...  Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective.  ...  In other words, we duplicate the tag-drive lines with only half-long length of tag-drive lines onto each layer and thus lowered wire capacitance can be acquired.  ... 
doi:10.1109/vlsid.2007.41 dblp:conf/vlsid/VaidyanathanHWXNI07 fatcat:5xdu5aioabevpd5gs4codh5qxe

Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI

E.G. Friedman, S. Powell
1986 IEEE Journal of Solid-State Circuits  
In particular, a bierarcbicat design technique for minimizing clock skew within a VLSI circuit and its relative advantages and disadvantages is discussed.  ...  In addition, a model for clock distribution networks which considers the effects of dktributed interconnect impedances on clock skew is described.  ...  Persky for his sincere encouragement and advice in writing this paper.  ... 
doi:10.1109/jssc.1986.1052510 fatcat:xyseq6llfjh5rmucmoliagossa

Clock distribution networks in synchronous digital integrated circuits

E.G. Friedman
2001 Proceedings of the IEEE  
A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths.  ...  The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated  ...  A common feature of these VLSI-based multipliers (and many VLSI-based systems) is the repetitive organization of the physical layout.  ... 
doi:10.1109/5.929649 fatcat:eppzijpvzncvnpjzkgenkug6ni

Retrospective on VLSI value scaling and lithography

Michael L. Rieger
2019 Journal of Micro/Nanolithography  
On top of the miniaturization benefits delivered by optical lithography, value is boosted by innovations in wafer processing, mask synthesis, materials and devices, microarchitecture, and circuit design  ...  Focusing on three decades of microprocessor data enables quantification of how innovations from those domains have contributed over time to integrated-circuit "value scaling" in terms of performance, power  ...  Thanks also to Jamil Kawa, Synopsys, for his review of this paper from a VLSI design perspective.  ... 
doi:10.1117/1.jmm.18.4.040902 fatcat:2gpl7npferd2hp5wpkjpte4xmm

Area penalty for sublinear signal propagation delay on chip

Paul M. B. Vitanyi
1985 26th Annual Symposium on Foundations of Computer Science (sfcs 1985)  
Thus, the overall efficiency of many very large scale integrated (VLSI) electronic switching circuits depends strongly on the signal propagation delay in long wires.  ...  In designing such a high speed layout we therefore need to install drivers to drive the long wires and to design all wires with a constant aspect ratio a >O.  ... 
doi:10.1109/sfcs.1985.10 dblp:conf/focs/Vitanyi85 fatcat:zuq4k4espjamdddoq7ob7owvzm

Contrasts in Physical Design between LSI and VLSI

W.R. Heller
1981 18th Design Automation Conference  
With all this growth, a l t e r n a t i v e s in VLSI design style as well as packaging have to be considered.  ...  u e s facilitating rapid, i n t e r a c t i v e a d a p t a t i o n of f u n c t i o n a l logic design to the layout and i n t e r c o n n e c t i o n of "macros" on large chips.  ...  Examples are: (a) fan-out or wire length limits due to device drive capability, (b) wire length minima or cluster configurations set by line reflections of voltage pulses, (c) noise coupling from extended  ... 
doi:10.1109/dac.1981.1585426 fatcat:7wu2j5ur3ncizenzbjekbibvz4

Design of a High Performance VLSI Processor [chapter]

John L. Hennessy, Norman P. Jouppi, Steven Przybylski, Christopher Rowen, Thomas Gross
1983 Third Caltech Conference on Very Large Scale Integration  
Current VLSI fabrication technology makes it possible to design a 32-bit CPU on a single chip.  ...  The MIPS processor incorporates some new architectural ideas into a single-chip, nMOS implementation.  ...  Acknowledgments Many people have contributed to the MIPS project; especially worthy of note are John Gill, Forest Baskett, and Jud Leonard.  ... 
doi:10.1007/978-3-642-95432-0_3 fatcat:ga53jb5k2zhphn7wju25yweh7u
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