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A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors

Paul Beckett
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The logic function operating on the first gate of a double-gate (DG) transistor is reconfigured by altering the charge on its second gate.  ...  of Electrical and Computer Engineering, RMIT University, where he teaches undergraduate and postgraduate courses in embedded computer architecture, digital logic, and VLSI design.  ...  In the example of Fig. 10 , the nine inputs are partitioned across cells 1, 3, and 5. Cell 1 creates the logic function (normal threshold for these three inputs, high for the remaining three).  ... 
doi:10.1109/tvlsi.2007.912024 fatcat:6guwuhgv2zao7fxbkewfqyps7u

Device scaling limits of Si MOSFETs and their application dependencies

D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, Hon-Sum Philip Wong
2001 Proceedings of the IEEE  
, VT, to work on 1-Mb DRAM, and then began work on sub-half-micron MOSFETs for logic in 1984.  ...  in which application-related considerations enter into the determination of these limits.  ...  ACKNOWLEDGMENT The authors would like to thank the invaluable contributions of many of their colleagues, including E. Jones, L. Huang, and G. Cohen for their collaboration on DG-FET research, M.  ... 
doi:10.1109/5.915374 fatcat:r4tvpqmqofgrfg2zuxhrtjwpqe

Power-constrained CMOS scaling limits

D. J. Frank
2002 IBM Journal of Research and Development  
The details of these effects, along with other scaling issues, are discussed in the context of their dependence on application.  ...  The scaling of CMOS technology has progressed rapidly for three decades, but may soon come to an end because of powerdissipation constraints.  ...  Acknowledgment This work has benefited greatly from many useful discussions with co-workers and colleagues, including especially the collaborators on Reference [1] : Bob Dennard, Ed Nowak, Paul Solomon  ... 
doi:10.1147/rd.462.0235 fatcat:ktxzz5yjoffc3civ6uelepesga

Graph-based quantum logic circuits and their realization by novel GaAs multiple quantum wire branch switches utilizing Schottky wrap gates

Miki Yumoto, Seiya Kasai, Hideki Hasegawa
2002 Microelectronic Engineering  
A novel approach for quantum logic circuits is described. In this approach, graph-based circuits are directly constructed on nanowire networks and controlled by multiple quantum wire branch switches.  ...  Potential advantages of the approach are briefly discussed.  ...  In each case, logic value of 1 or 0 of the logic function is determined whether the messenger starting from the root terminal reaches termnal-1 or terminal-0.  ... 
doi:10.1016/s0167-9317(02)00615-9 fatcat:sxah7dk5xzdyvmhrif6wvxhdmy

Spin Wave Based Approximate 4:2 Compressor [article]

Abdulqader Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Said Hamdioui, Sorin Cotofana
2021 arXiv   pre-print
We validate our proposal by means of micromagnetic simulations, and assess and compare its performance with one of the state-of-the-art SW, 45nm CMOS, and Spin-CMOS counterparts.  ...  When compared with the other emerging technologies, the proposed compressor outperforms approximate Spin-CMOS based compressor by 3 orders of magnitude in term of energy consumption while providing the  ...  However, in this paper, we Threshold detection relies on the comparison of the output SW amplitude with a predefined threshold value T , i.e., if the SW amplitude is larger than T , the output is logic  ... 
arXiv:2109.09554v1 fatcat:w4wiroo2dbf4leilkx7m4eb65y

Hardware Implementation of Fuzzy Controllers [chapter]

Victor Varshavsky, Viacheslav Marakhovsky, Ilya Levin, Hiroshi Saito
2011 Fuzzy Controllers, Theory and Applications  
Then the table of fuzzy rules will to determine by obvious way the function of multi-valued logic, values of which define the digit representation of the output linguistic variable on chosen value combinations  ...  approximation between a couples of points calculated as adjacent values of a multi-valued logic function.  ... 
doi:10.5772/13414 fatcat:jonbn2hrffeale535ghpsrc4mq

Low Power and High Performance VLSI Interconnects By Schmitt Trigger Technique In Nanoscale Regime

R.S.G Bhavani, M Manikumari, Dr. K.Padma priya
2014 IOSR Journal of VLSI and Signal processing  
In this work replacement of sized logic with buffers with Schmitt trigger based on sizing is proposed for the signal restoration and to reduce delay.  ...  Because of adjustable threshold voltage V th of Schmitt trigger the delay and power can be reduced in interconnects when compared to buffers.  ...  This value can be high i.e a few nanoseconds depending on the values of resistance and parasitic capacitance.  ... 
doi:10.9790/4200-04524047 fatcat:kyke7ri7bnbppmfl6fkhy52k2e

BTI reliability of ultra-thin EOT MOSFETs for sub-threshold logic

J. Franco, S. Graziano, B. Kaczer, F. Crupi, L.-Å. Ragnarsson, T. Grasser, G. Groeseneken
2012 Microelectronics and reliability  
A first study of the BTI reliability of a 6 Å EOT CMOS process for potential application in sub-threshold logic is presented.  ...  A proper device failure criterion is proposed, based on simulation of the DC robustness of an inverter logic circuit.  ...  Acknowledgement This work was performed as part of IMEC's Core Partner Program.  ... 
doi:10.1016/j.microrel.2012.06.058 fatcat:rgsepicxxfg4zfidsrpc2tqjqa

CMOS-based carbon nanotube pass-transistor logic integrated circuits

Li Ding, Zhiyong Zhang, Shibo Liang, Tian Pei, Sheng Wang, Yan Li, Weiwei Zhou, Jie Liu, Lian-Mao Peng
2012 Nature Communications  
In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n-and pfield-effect  ...  Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration  ...  Acknowledgements We would like to thank Professor Xu Cheng for valuable discussions on the passtransistor logic.  ... 
doi:10.1038/ncomms1682 pmid:22334080 pmcid:PMC3293427 fatcat:mncoymjahnfencqudhropdetju

FPGA challenges and opportunities at 40nm and beyond

Vaughn Betz
2009 2009 International Conference on Field Programmable Logic and Applications  
FPGA companies are amongst the earliest adopters of next-generation integrated circuit process technology, as the economics of scaling are more favorable for FPGAs than for many other technologies.  ...  In this paper, we highlight the economic and technological advantages of moving FPGAs to more advanced processes, and discuss the techniques Altera is using to overcome the challenges that come with process  ...  Stratix IV Overview Altera's Stratix IV FPGA was delivered in 2008, making it both the first 40 nm FPGA and one of the first 40 nm devices of any type.  ... 
doi:10.1109/fpl.2009.5272567 dblp:conf/fpl/Betz09 fatcat:vs5nsugg5ve2heqfnv4si3xnzu

Fanout of 2 Triangle Shape Spin Wave Logic Gates [article]

Abdulqader Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
2021 arXiv   pre-print
The proposed logic gates are validated by means of micromagnetic simulations.  ...  This paper proposes novel triangle shape fanout of 2 spin wave Majority and XOR gates; the Majority gate is achieved by phase detection, whereas the XOR gate is achieved by threshold detection.  ...  Likewise, the dimensions of the device in Figure 3 can be determined to be d 1 =330 nm, and d 2 =40 nm.  ... 
arXiv:2011.11324v5 fatcat:w3bw57pq2ndcxpj6urg4ducg3e

The fundamental downscaling limit of field effect transistors

Denis Mamaluy, Xujiao Gao
2015 Applied Physics Letters  
Impact of the top silicon thickness on phonon-limited electron mobility in (110)-oriented ultrathin-body silicon-oninsulator n -metal-oxide-semiconductor field-effect transistors Limitations on threshold  ...  Articles you may be interested in Corner effects on phonon-limited mobility in rectangular silicon nanowire metal-oxide-semiconductor field-effect transistors based on spatially resolved mobility analysis  ...  other significant technological challenges could be addressed in one way or another.  ... 
doi:10.1063/1.4919871 fatcat:ehd2sku5ojgyhkuoiw4x2n5vvy

Performance Based Comparative Analysis of MOS Structures at 32nm and 20nm Node
IJARCCE - Computer and Communication Engineering

Pallavi Choudhary, Tarun Kapoor
2015 IJARCCE  
The structures have been fabricated using SILVACO TCAD software and study of threshold voltages and corresponding oxide thickness has been made.  ...  This is guided by decrease in the gate length or channel length. However decrease in channel length of planar MOSFETs has reached its saturation level due to short channel effects and DIBL.  ...  bias present, and V T0 is the zero-V SB value of threshold voltage, is the body effect parameter, and 2φ B is the approximate potential drop between surface.  ... 
doi:10.17148/ijarcce.2015.4334 fatcat:plbujh5jbzbmveg5krn6eaoyhi

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies

Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2014 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory.  ...  In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process.  ...  A sufficient approximation for an equivalent threshold voltage is V ON = i ON • R OFF (11) where V ON is the voltage threshold, and i ON is the current threshold.  ... 
doi:10.1109/tvlsi.2013.2282132 fatcat:difloz36prcdjkgymd67lriede

Writing wavy metal 1 shapes on 22-nm logic wafers with less shot count

Harold R. Zable, Aki Fujimura, Tadashi Komagata, Yasutoshi Nakagawa, John S. Petersen, Kunihiro Hosono
2010 Photomask and Next-Generation Lithography Mask Technology XVII  
The metal 1 layer for the 22 nm logic node will require complex "wavy" shapes. These shapes are decorations on main features and require highly accurate printing in order to meet CD requirements.  ...  It incorporates e-beam simulation as an integrated part in order to determine the dose and shape of the overlapping shots to draw complex mask shapes with less shot count.  ...  ACKNOLEDGEMENTS Authors would like to thank the people of JEOL Ltd. and D2S, Inc. for their efforts, and Ingo Bork of D2S for his help in preparation of the manuscript.  ... 
doi:10.1117/12.866971 fatcat:5mwlwxoq2jchrbnyafowmuillu
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