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SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures
[chapter]
2014
Lecture Notes in Computer Science
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The increasing availability of different kinds of processing resources in heterogeneous system architectures associated with today's fast-changing, unpredictable workloads has propelled an interest towards ...
Self-adaptiveness and hardware-assisted virtualization are the two key-enabling technologies for this kind of architectures, to allow the efficient exploitation of the available resources based on the ...
Another advantage is the usage of a common virtual memory system for host processors and accelerators, to allow accelerators to access virtual memory addresses that are not yet available in the physical ...
doi:10.1007/978-3-319-05960-0_38
fatcat:txyxyy3oxfgxxlejazrypktzti
Dynamic heterogeneity and the need for multicore virtualization
2009
ACM SIGOPS Operating Systems Review
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As the computing industry enters the multicore era, exponential growth in the number of transistors on a chip continues to present challenges and opportunities for computer architects and system designers ...
We show that multicore virtualization operates with minimal overhead, and that it enables several novel resource management applications for improving both performance and reliability. ...
Morgridge Chair in Computer Sciences and the University of Wisconsin Graduate School. Sohi has a significant financial interest in Sun Microsystems. ...
doi:10.1145/1531793.1531797
fatcat:mgrtesoh7zawjf7potq6nc2wmq
The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling
2008
IEEE Micro
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These designs have been ad hoc in nature, and there is significant opportunity for the OS community to apply their accumulated knowledge and experience to this problem. ...
We are also trying to exploit aspects of the vast amount of prior work in load balancing for traditional multichip multiprocessors and distributed systems. ...
Bower is a senior engineer in the Systems and Technology Group at IBM, and is pursuing his PhD in computer science at Duke University. ...
doi:10.1109/mm.2008.46
fatcat:34i2x4grd5hhzb64uuue4ebj7y
An Evaluation of Server Consolidation Workloads for Multi-Core Designs
2007
2007 IEEE 10th International Symposium on Workload Characterization
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Such server consolidation scenarios will simplify system administration and lead to savings in power, cost, and physical infrastructure. ...
In the meantime, one sure-fire application for such machines will be to serve as consolidation platforms for sets of workloads that previously occupied multiple discrete systems. ...
Acknowledgments We would like to thank our anonymous reviewers for their helpful feedback and in particular Ravi Iyer for his suggestions on this work. ...
doi:10.1109/iiswc.2007.4362180
dblp:conf/iiswc/JergerVL07
fatcat:emv722pbfza3zflixvt67the34
High-Performance Embedded Architecture and Compilation Roadmap
[chapter]
2007
Lecture Notes in Computer Science
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technology for high-performance embedded systems. ...
(vi) runtime systems, (vii) benchmarking, (viii) simulation and system modeling, (ix) reconfigurable computing, and (x) real-time systems. ...
shared memory. ...
doi:10.1007/978-3-540-71528-3_2
fatcat:ywmebvj7wrfb3ojghsjs4w3fy4
HeteroOS
2017
SIGARCH Computer Architecture News
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To address this, we design HeteroOS, a novel application-transparent OS-level solution for managing memory heterogeneity in virtualized system. ...
Heterogeneous memory management combined with server virtualization in datacenters is expected to increase the software and OS management complexity. ...
Department of Energy and Intel Labs for their funding and access to the Intel NVM emulator platform. ...
doi:10.1145/3140659.3080245
fatcat:7ezgmsbtivc4hpd6zhsbviuyde
Research Problems and Opportunities in Memory Systems
2014
Supercomputing Frontiers and Innovations
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memory systems), 3) providing predictable performance and QoS to applications sharing the memory system (i.e., QoS-aware memory systems). ...
The memory system is a fundamental performance and energy bottleneck in almost all computing systems. ...
We would like to thank Rachata Ausavarungnirun for logistic help in preparing this article and earlier versions of it. ...
doi:10.14529/jsfi140302
fatcat:2zfa7zk3qjgohdsgxmkkqaamuu
Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
2013
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Such a heterogeneous DRAM chip provides a unique, promising opportunity for computer architects to contemplate a new memory hierarchy for future system design. ...
In this paper, we study how to design such a heterogeneous DRAM chip for improving both performance and energy efficiency. ...
In this paper, we investigate a heterogeneous memory architecture as the first step to exploit the opportunities for performance and energy. ...
doi:10.1109/tvlsi.2011.2176761
fatcat:tgdsehnjife6rawz36td74vquu
Evaluating Cache Coherent Shared Virtual Memory for Heterogeneous Multicore Chips
[article]
2013
arXiv
pre-print
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Although current homogeneous chips tightly couple the cores with cache-coherent shared virtual memory (CCSVM), this is not the communication paradigm used by any current HMC. ...
The trend in industry is towards heterogeneous multicore processors (HMCs), including chips with CPUs and massively-threaded throughput-oriented processors (MTTOPs) such as GPUs. ...
Cache-Coherent Shared Virtual Memory The key aspect of our architecture is to extend CCSVM from homogeneous to heterogeneous chips.
Shared Virtual Memory (SVM) Architecture. ...
arXiv:1310.7792v1
fatcat:vyzvw7cetjfzhawfivoabw7g44
Jenga
2017
SIGARCH Computer Architecture News
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These overheads are expensive on emerging systems with heterogeneous memories, where the differences in latency and energy across levels are small. ...
Jenga builds virtual cache hierarchies out of heterogeneous, distributed cache banks using simple hardware mechanisms and an OS runtime. ...
This work was supported in part by NSF grants CCF-1318384 and CAREER-1452994, a Samsung GRO grant, and a grant from the Qatar Computing Research Institute. ...
doi:10.1145/3140659.3080214
fatcat:l76s4gki7jfidcaqwfe7noddu4
EXOCHI
2007
SIGPLAN notices
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In this paper, we present EXOCHI: (1) Exoskeleton Sequencer (EXO), an architecture to represent heterogeneous accelerators as ISA-based MIMD architecture resources, and a shared virtual memory heterogeneous ...
On the EXO prototype system, we have enhanced a suite of production-quality media kernels for video and image processing to utilize the accelerator through the CHI programming interface, achieving significant ...
Acknowledgments We would like to thank John Shen, Rich Hankins Khandelwal, and the anonymous reviewers whose valuable feedback has helped the authors greatly improve the quality of this paper. ...
doi:10.1145/1273442.1250753
fatcat:kecpgrwcaneopjizq6iorj5wla
EXOCHI
2007
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation - PLDI '07
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In this paper, we present EXOCHI: (1) Exoskeleton Sequencer (EXO), an architecture to represent heterogeneous accelerators as ISA-based MIMD architecture resources, and a shared virtual memory heterogeneous ...
On the EXO prototype system, we have enhanced a suite of production-quality media kernels for video and image processing to utilize the accelerator through the CHI programming interface, achieving significant ...
Acknowledgments We would like to thank John Shen, Rich Hankins Khandelwal, and the anonymous reviewers whose valuable feedback has helped the authors greatly improve the quality of this paper. ...
doi:10.1145/1250734.1250753
dblp:conf/pldi/WangCCJTGYLW07
fatcat:72glznuq4zewfl3iezwdzggsum
Supporting Address Translation for Accelerator-Centric Architectures
2017
2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)
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First, to support bulk transfers of consecutive data between the scratchpad memory of customized accelerators and the memory system, we present a relatively small private TLB design to provide low-latency ...
Second, to compensate for the effects of the widely used data tiling techniques, we design a shared level-two TLB to serve private TLB misses on common virtual pages, eliminating duplicate page walks from ...
ACKNOWLEDGMENT We thank the anonymous reviewers for their feedback. ...
doi:10.1109/hpca.2017.19
dblp:conf/hpca/HaoFRC17
fatcat:cqywaosz3rddnkm4aiehc674cu
Shared Virtual Reality for Architectural Design
[chapter]
1997
CAAD futures 1997
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The paper presents the implementation of a system of Shared Virtual Reality (SVR) in Internet applied to a large-scale project. ...
SVR differs from Virtual Reality in that the experience of virtual spaces is no longer individual, but rather shared across the net with other users simultaneously connected. ...
Acknowledgements Participating to the project are: Councillor for special projects, ...
doi:10.1007/978-94-011-5576-2_32
fatcat:vnehcypye5dupc2g5tlqbhe4xu
Harnessing ISA diversity
2014
SIGARCH Computer Architecture News
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Architects have explored multiple dimensions of heterogeneity, both in terms of micro-architecture and specialization. ...
Heterogeneous multicore architectures have the potential for high performance and energy efficiency. ...
Acknowledgements The authors would like to thank the anonymous reviewers for their helpful insights. This research was supported in part by NSF Grants CCF-1219059 and CCF-1302682. ...
doi:10.1145/2678373.2665692
fatcat:s2iurlomofbfficeone5inbz3q
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