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This paper presents a binary acceleration approach based on extending a General Purpose Processor (GPP) with a Reconfigurable Processing Unit (RPU), both sharing an external data memory. In this approach repeating sequences of GPP instructions are migrated to the RPU. The RPU resources are selected and organized off-line using execution trace information. The RPU core is composed of Functional Units (FUs) that correspond to single CPU instructions. The FUs are arranged in stages of mutuallydoi:10.1109/ispa.2014.29 dblp:conf/ispa/PaulinoFC14 fatcat:u3mcgsqss5cf5lzno7pzbustga