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A Novel Co-Design Approach for Soft Errors Mitigation in Embedded Systems
2011
IEEE Transactions on Nuclear Science
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A novel proposal to design radiation-tolerant embedded systems combining hardware and software mitigation techniques is presented. ...
Two suites of tools are developed to automatically apply the techniques and to facilitate the tradeoffs analyses. ...
CONCLUSIONS AND FUTURE WORK This paper presents a novel approach to design fault tolerant embedded systems. ...
doi:10.1109/tns.2011.2112379
fatcat:cgrd47chdvc43dm7d2e72tdpfe
Evolution of Test Programs Exploiting a FSM Processor Model
[chapter]
2011
Lecture Notes in Computer Science
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A novel evolutionary-based approach, able to appreciably reduce the generation time, is presented. ...
The proposed method exploits a high-level representation of the architecture under test and a dynamically built Finite State Machine (FSM) model to assess fault coverage without resorting to timeexpensive ...
We would like to thank Danilo Ravotto and Xi Meng for technical assistance during experimental evaluation. ...
doi:10.1007/978-3-642-20520-0_17
fatcat:hkisugw2mffqtpprrzpv2adgnm
New evolutionary techniques for test-program generation for complex microprocessor cores
2005
Proceedings of the 2005 conference on Genetic and evolutionary computation - GECCO '05
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The approach is suitable for medium-sized processor cores. ...
The experimental evaluation performed on a SPARCv8 clearly shows the potentiality of the approach, and the effectiveness of the enhancements to the evolutionary core. ...
a novel approach for the automatic completion of a test suite for a medium-sized microprocessor core. ...
doi:10.1145/1068009.1068370
dblp:conf/gecco/SanchezSRSSV05
fatcat:nytyo46mafbqpnaqpzrzfvwztm
Design of a high reliability self diagnosing computer using bit slice microprocessors
1988
Microprocessing and Microprogramming
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Innovative techniques were used to achieve high performance without using very high reliability components or redundancy at the circuit level. ...
This paper describes a processor built to meet the requirements for a highly reliable and ruggedised digital computer. ...
its performance. ...
doi:10.1016/0165-6074(88)90401-2
fatcat:5bmy3at47fd2bcoqkk74zrs5qy
Low-Cost Protection for SER Upsets and Silicon Defects
2007
2007 Design, Automation & Test in Europe Conference & Exhibition
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By utilizing low-cost techniques to address defects and SER, we keep protection costs significantly lower than traditional fault-tolerance approaches while providing high levels of coverage for a wide ...
The approach works by periodically testing the processor to determine if the system is broken. If so, we reconfigure the processor to avoid using the broken component. ...
TRANSIENT FAULT PROTECTION We propose a novel circuit for transient fault detection, based on a double-sampling scan flip-flop. ...
doi:10.1109/date.2007.364449
fatcat:3w6pm3mygzegjmgnjn54ijarwq
Efficient testing of clock regenerator circuits in scan designs
1997
Proceedings of the 34th annual conference on Design automation conference - DAC '97
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This paper describes the use of a high-level view (functional view) of a clock regenerator circuit for generating effective and inexpensive manufacturing tests. ...
A test generation procedure is described and successfully used on a microprocessor design. ...
Finally, our thanks goes to Carlos Gutierrez and Mark McDermott for providing management support in completing this work. ...
doi:10.1145/266021.266042
dblp:conf/dac/RainaBNMB97
fatcat:fb3phlopgreo3dv3wwht2apq24
Testability features of the AMD-K6 microprocessor
1998
IEEE Design & Test of Computers
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signs and manufactures x86-compatible microprocessors, continually improving performance and functionality in step with evolving markets and emerging functional enhancements to the x86 instruction set. ...
We incorporated builtin self-test (BIST) in all major internal, fullcustom functional blocks and used a novel I DDQ pattern generation approach. ...
MICROPROCESSOR TESTING Cell library development. Most cell library models used for single stuck-at-fault test pattern generation can also be used for path delay fault ATPG. ...
doi:10.1109/54.706035
fatcat:m622tzx4p5dtzhpin5jnuopjlu
Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA
2010
2010 International Conference on Field Programmable Logic and Applications
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In this context, the main contribution of this work is a novel rapid prototyping approach for the codesign of dependable embedded systems using FPGA. ...
This is supported by a hardening platform that allows combining software-only fault-tolerance techniques with hardware-only approaches, representing several trade-offs among design constraints, reliability ...
For each test program in the benchmark, non-hardened (O) and hardened (H), and for each approach of the microprocessor (P0 to P4), a fault injection campaign has been executed in the FTUnshades. ...
doi:10.1109/fpl.2010.71
dblp:conf/fpl/Restrepo-CalleMPGAC10
fatcat:v2q2ufkgnrdercyjh2iiiygmae
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs
[chapter]
2008
Design, Automation, and Test in Europe
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This paper presents a novel cost-effective approach to the construction of diagnostic software-based test sets for microprocessors. ...
The methodology exploits an existing post-production test set, designed for software-based self-test, and an already developed infrastructure IP to perform the diagnosis. ...
EC size
Post
Conclusions and future work A novel automated approach for the generation of software-based diagnostic sets for microprocessors has been presented. ...
doi:10.1007/978-1-4020-6488-3_36
fatcat:out2igktqverjgiu7c2l66myqa
Compiler-Directed Soft Error Mitigation for Embedded Systems
2012
IEEE Transactions on Dependable and Secure Computing
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At the same time, for large segments of embedded markets, parameters like cost and performance continue to be as important as reliability. ...
Several trade-offs among performance, code size, reliability, and hardware costs have been explored. Results show the applicability of the approach. ...
Notice that the high fault coverage results obtained for the unprotected versions is due to the fact that the fault injection test was performed over the complete register file, even though the programs ...
doi:10.1109/tdsc.2011.54
fatcat:72lpyhcoi5eozhneoj3cth74wa
Microcontroller Based Testing of Digital IP-Core
2012
International Journal of VLSI Design & Communication Systems
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Testing core based System on Chip is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. ...
The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores . The prominent feature of the approach is to use microcontroller to test IP-core. ...
The novel approach is to test the each IP-core separately. IP-core consists of microprocessors (MP), microcontroller (MC), memories, ASICs, and peripherals. Here digital IP-core is used for testing. ...
doi:10.5121/vlsic.2012.3205
fatcat:kh627wxg3fd67fotzhobdhhs4a
On testing timing-speculative circuits
2013
Proceedings of the 50th Annual Design Automation Conference on - DAC '13
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In this paper, we propose novel techniques to achieve high fault coverage for timing-speculative circuits without incurring high designfor-testability cost. ...
How to effectively test timingspeculative circuits, however, has not been addressed in the literature. ...
Without adding dedicated DfT circuits for such faults, we discuss how to achieve high fault coverage by novel test application techniques after introducing our test strategies for static faults in EGP ...
doi:10.1145/2463209.2488771
dblp:conf/dac/YuanLJX13
fatcat:2djldylu75dunnhjeznfhhzq4i
Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors
2012
IEEE transactions on computers
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Global Signal Vulnerability (GSV) analysis is a novel method for assessing the susceptibility of modern microprocessor state elements to failures in the field of operation. ...
In order to effectively allocate design for reliability resources, GSV analysis takes into account the high degree of architectural masking exhibited in modern microprocessors and ranks state elements ...
For the Intel microprocessor, the closest checkpoint is loaded and a fault free simulation is performed until the desired clock cycle. ...
doi:10.1109/tc.2011.172
fatcat:6n2my6zva5fhjfofadxl7v4upq
Application-driven co-design of fault-tolerant industrial systems
2010
2010 IEEE International Symposium on Industrial Electronics
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This paper presents a novel methodology for the HW/SW co-design of fault tolerant embedded systems that pursues the mitigation of radiation-induced upset events (which are a class of Single Event Effects ...
Using the proposed methodology, the design was guided by the requirements of the application, leading us to explore several trade-offs among reliability, performance and cost. ...
The work presented here has been carried out thanks to the support of the research projects 'Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware: Aplicación al ...
doi:10.1109/isie.2010.5637483
fatcat:z4eavmlkonavvi5fbjggzi3odu
Asynchronous Design—Part 2: Systems and Methodologies
2015
IEEE design & test
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Part 2 focuses on methodologies for designing asynchronous systems, including basics of hazards, synthesis and optimization methods for both logic-level and high-level synthesis, and the development of ...
Finally, two sidebars provide a summary of asynchronous processors and architectures, as well as testing. ...
A novel approach to testing delay faults-in particular, timing constraint violations-in asynchronous pipelines has also been proposed. 9 Unlike synchronous approaches, very little testing hardware is ...
doi:10.1109/mdat.2015.2413757
fatcat:bpxnljdkofh6ppyovk6sp4pknm
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