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Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates
[chapter]
2009
Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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In this paper, it is shown that use of high-k dielectrics and metal gates increases the supply voltage where this reversal occurs by 40% compared to low-k, poly gate technologies. 45, 32, and 22 nm models ...
Adaptive voltage scaling, commonly used in variation-tolerant systems, further complicates the temperature impact, as the range of voltages may intersect both temperature regions. ...
Use of high-k dielectrics and metal gates to alleviate nanoscale gate leakage problems also alters V T and µ [4, 5] . ...
doi:10.1007/978-3-642-02427-6_4
fatcat:b2jfyinqmfaqjlcdx5pteyczku
High-performance CMOS variability in the 65-nm regime and beyond
2006
IBM Journal of Research and Development
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Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. ...
The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. ...
of International Business Machines Corporation. ** Trademark, service mark, or registered trademark of Nintendo in the United States, other countries, or both. ...
doi:10.1147/rd.504.0433
fatcat:ij2vpwacyzfvbfjumtpatz63wm
Beyond the conventional transistor
2002
IBM Journal of Research and Development
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These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. ...
Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. ...
Acknowledgments This paper is distilled from collaborations and discussions over the years with many colleagues too numerous to mention individually, both within IBM as well as in the academic community ...
doi:10.1147/rd.462.0133
fatcat:zwt2evpshjejlg7ulv5kvpl5za
Beyond the conventional transistor
2005
Solid-State Electronics
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These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. ...
Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. ...
Acknowledgments This paper is distilled from collaborations and discussions over the years with many colleagues too numerous to mention individually, both within IBM as well as in the academic community ...
doi:10.1016/j.sse.2004.10.014
fatcat:5lwilesg6vc5bmm6bdj3mh4m6u
High Performance CMOS Variability in the 65nm Regime and Beyond
2007
2007 IEEE International Electron Devices Meeting
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Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. ...
The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. ...
Acknowledgments We gratefully acknowledge contributions by Huifang Qin, Paul Friedberg, Ruth Wang (UC Berkeley) and Ronald Bolam (IBM Burlington, Vermont). ...
doi:10.1109/iedm.2007.4419002
fatcat:hfmoqtlzkfgajjmwqcsltnwg4u
2020 Index IEEE Transactions on Electron Devices Vol. 67
2020
IEEE Transactions on Electron Devices
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and Dixit, A., Character-ization and Modeling of Hot Carrier Degradation in N-Channel Gate-All-Around Nanowire FETs; TED Jan. 2020 4-10 Gupta, C., Gupta, A., Vega, R.A., Hook, T.B., and Dixit, A., Impact ...
Grasser, T., Mixed Hot-Carrier/Bias Temperature Instability Degradation Regimes in Full {V G , V D } Bias Space: Implications and Peculiarities; TED Aug. 2020 3315-3322 Jegadheesan, V., Sivasankaran, ...
of High-k Dielectric Layers. ...
doi:10.1109/ted.2021.3054448
fatcat:r4ertn5jordkfjjvorvss7n6ju
Molecular Electronics: From Physics to Computing
[article]
2005
arXiv
pre-print
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, logic systems and architectures. ...
Molecular nanostructures promise to occupy a prominent role in any attempt to extend charge-based device technology beyond the projected limits of CMOS scaling. ...
M.R. is also supported by the NSF Network for Computational Nanotechnology and the NASA URETI program. This paper is dedicated to Ned Seeman, visionary and friend. ...
arXiv:cond-mat/0508477v2
fatcat:cy4veyprwfauxof2lqvr4ssy3m
Structured Semiconductor Interfaces: Active Functionality on Light Manipulation
2019
Proceedings of the IEEE
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Plasmonic and dielectric metasurfaces have been intensively explored, building up the frameworks of flat optics for ultrathin and integrated nanophotonics. ...
, quantum optics, nano-optics, and surface engineering with full compatibility of semiconductor foundry. ...
It is composed of two metallic layers with a middle dielectric layer in between. ...
doi:10.1109/jproc.2019.2919675
fatcat:5dyqplqmgrcpvop3rcfilaybpi
Electric‐Field‐Controlled Antiferromagnetic Spintronic Devices
2020
Advanced Materials
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2021 pre-print arXiv:2108.04446v1 fatcat:qamqsyk7yveahazoninwjrwi7u
In conclusion, the possibility of realizing high-quality room-temperature antiferromagnetic tunnel junctions, antiferromagnetic spin logic devices, and artificial antiferromagnetic neurons is highlighted ...
modulation with respect to antiferromagnets are examined. ...
The magnetic spin Hall and inverse spin Hall effects only appear in time-symmetry-broken systems, i.e., magnetic systems, and must be odd under time reversal. ...
doi:10.1002/adma.201905603
pmid:32048366
fatcat:cmpwenklrbbnxbd5lbyve5ogzi
Semiconductor nanowires
2006
Journal of Physics D: Applied Physics
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Semiconductor nanowires (NWs) represent a unique system for exploring phenomena at the nanoscale and are also expected to play a critical role in future electronic and optoelectronic devices. ...
Room-temperature high-performance electrical and optical devices will then be discussed at the single-or few-nanowire level. ...
Acknowledgments The authors are indebted to the assistance from many of their colleagues at the University of Michigan and Harvard University. ...
doi:10.1088/0022-3727/39/21/r01
fatcat:jzljb5hlffaydmjf22veouqgku
Analysis of current–voltage–temperature characteristics in SiC Schottky diodes using threshold-accepting simulated-annealing techniques
2007
Solid-State Electronics
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Schottky barriers to WBG semiconductors are attractive in particular for high temperature/high power diodes, photodetectors, and gas sensors. ...
The work presented in this thesis comprises of two parts. Part I deals with Schottky contacts to the wide bandgap (WBG) semiconductors SiC, GaN and ZnO. ...
The DUT is first cooled to a low temperature (∼ 100 K) and at a fixed temperature, the DUT is held at a constant reverse bias. ...
doi:10.1016/j.sse.2007.03.008
fatcat:pizwxm2j6nhwbgxhd3uh7eblde
Proximitized Materials
[article]
2018
arXiv
pre-print
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Advances in scaling down heterostructures and having an improved interface quality together with atomically-thin two-dimensional materials suggest a novel approach to systematically design materials. ...
While the focus is on magnetic and spin-orbit proximity effects with their applications in spintronics, the outlined principles provide also a broader framework for employing other proximity effects to ...
(i) Local bottom gate electrode with Ni as the
metal electrode and ZrO 2 as the gate dielectric. ...
arXiv:1805.07942v1
fatcat:idxjndafvbhfxjxlnvavkv5p4y
Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners
2009
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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Optimized in a 90-nm 1.2/2.5-V CMOS process with practical issues taken into account, the LNA using a constant-bias circuit achieves competitive and robust performances over process, voltage and temperature ...
The amplification core exploiting double current reuse and single-stage thermal-noise cancellation enhances the gain and noise performances with high power efficiency. ...
ACKNOWLEDGMENT The authors would like to thank the Editor-in-Chief, the Associate Editor, and the anonymous reviewers for their insightful comments and K.-H. ...
doi:10.1109/tcsi.2009.2015185
fatcat:td6pjrhsdndl7pkttc5osqprmi
Device scaling limits of Si MOSFETs and their application dependencies
2001
Proceedings of the IEEE
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The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. ...
and high-performance CMOS logic. ...
Naveh and K. Likharev for useful discussions about the limits of DG-FET scaling and for access to several of their preprints and H. Kawaura for kindly providing original versions of his figures. ...
doi:10.1109/5.915374
fatcat:r4tvpqmqofgrfg2zuxhrtjwpqe
Toward Valley-coupled Spin Qubits
[article]
2020
arXiv
pre-print
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Such valley-coupled spins are protected by inversion asymmetry and time-reversal symmetry and are promising candidates for robust qubits. ...
In the recent decade, valleytronics has seen a revival due to the discovery of valley-coupled spins in monolayer transition metal dichalcogenides. ...
(c) Schematic of locally gated nanoribbon device to tune out defect states and provide controlled quantum dot in nanoribbon (with local metallic top-gates separated from nanoribbon by a dielectric layer ...
arXiv:2004.06007v2
fatcat:ozrq3i5hvrgvzo73poi6tbuueq
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