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Architectural considerations for application-specific counterflow pipelines

B.R. Childers, J.W. Davidson
1999 Proceedings 20th Anniversary Conference on Advanced Research in VLSI  
Sutherland, Sproull, and Molnar have proposed a new pipeline organization called the Counterflow Pipeline (CFP).  ...  As an example, the 4-way superscalar HP PA-8000 microprocessor [17] tolerates a cache miss penalty of 50 clock cycles, which may cause the processor to stall for up to 200 instructions.  ...  Figure 12 gives insight into the performance of counterflow pipelines relative to modern computer architectures.  ... 
doi:10.1109/arvlsi.1999.756034 dblp:conf/arvlsi/ChildersD99 fatcat:sm2hu2vhrvghjeifj2ca3p7zem

A design environment for counterflow pipeline synthesis [chapter]

Bruce R. Childers, Jack W. Davidson
1998 Lecture Notes in Computer Science  
The Counterflow Pipeline (CFP) organization may be a good target for synthesis of application-specific microprocessors for embedded systems because it has a regular and simple structure.  ...  Instead, we customize a counterflow pipeline micro-architecture to an application using a standard RISC instruction set and information about the data flow of the target application.  ...  A clock cycle for the counterflow pipeline is a very small time unit such as a few gate delays. The instruction set we use is a subset of the SPARC V8 [14] instruction set architecture.  ... 
doi:10.1007/bfb0057793 fatcat:hxofcdqc6rg7rgtty5wjszxvra

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Joseph Crop, Evgeni Krimer, Nariman Moezzi-Madani, Robert Pawlowski, Thomas Ruggeri, Patrick Chiang, Mattan Erez
2011 Journal of Low Power Electronics and Applications  
While the main focus of this survey is on circuit approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well.  ...  For example, architectural level techniques will provide error protection while using non-protected circuits, and algorithm level approaches can offer error protection while operating on commodity (non-protected  ...  Figure 8 . 8 (a) Pipeline modification for Counterflow Pipelining error recovery method; (b) Counterflow pipeline data path with errors.  ... 
doi:10.3390/jlpea1030334 fatcat:5hwevwjj2fbzvaeume46u7nuom

Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction

Matthew Fojtik, David Fick, Yejoong Kim, Nathaniel Pinckney, David Money Harris, David Blaauw, Dennis Sylvester
2013 IEEE Journal of Solid-State Circuits  
A local stalling technique that can be automatically inserted into any design allows the system to scale to larger processors.  ...  We propose Bubble Razor, an architecturally independent approach to timing error detection and correction that avoids hold-time issues and enables large timing speculation windows.  ...  In both counterflow pipelining and architectural replay, the architecture is designed with Razor in mind and the correction mechanism is built into the RTL of the design.  ... 
doi:10.1109/jssc.2012.2220912 fatcat:m5zdao6ozrbklcu52rc4eoa5q4

Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis

Mario R. Casu, Luca Macchiarulo
2009 Electronical Notes in Theoretical Computer Science  
On the other hand, the antitoken on input c is free to propagate in counterflow.  ...  Since A's output has no token (A stalled because of the previous B's stall), the stop effect is null.  ... 
doi:10.1016/j.entcs.2009.07.027 fatcat:tfnakhg3pzhtvnteoal5twdugq

O2C

Swaroop Ghosh, Jung-Hwan Choi, Patrick Ndai, Kaushik Roy
2008 Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08  
ABSTRACTS In this paper, we propose O 2 C, a novel non-speculative adaptive thermal management technique that reduces the temperature during die-overheating using supply voltage scaling, while maintaining  ...  Two-cycle operation is achieved by stalling the pipeline for extra clock cycles whenever the set of critical paths are activated.  ...  Stalling can be achieved by several means e.g., nop insertion, gating the clock pulse, counterflow pipelining [11] etc.  ... 
doi:10.1145/1393921.1393971 dblp:conf/islped/GhoshCNR08 fatcat:anr6n3bfcvdexffuy5bq4wyn64

Razor

Todd Austin
2006 Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06  
We found that during normal (error-free) operation of the pipeline, Razor error detection increases pipeline energy demands by a modest 3.1%, compared to a non-Razor design of the architecture.  ...  Instructions IF ID EX MEM stall Correct value provided to MEM MEM Razor latch gets correct EX value ST ST ST ST ST stall Table 1 . 1 Energy-Optimal Characteristics Program  ... 
doi:10.1145/1150343.1150348 dblp:conf/sbcci/Austin06a fatcat:ts3b7k46kvf7hbk6wicbxi3d7q

Exploiting locality to improve circuit-level timing speculation

Jing Xin, R. Joseph
2009 IEEE computer architecture letters  
After a long interval of non-use, instructions which were once critical often become non-critical on subsequent execution.  ...  In essence, the counterflow pipeline recovery used in Razor designs is sensitive to the pipeline depth of timing errors.  ... 
doi:10.1109/l-ca.2009.50 fatcat:cvzsvdypyndg7fhgeex2ba4ilq

A distributed colouring algorithm for control hazards in asynchronous pipelines

T. Theodoropoulos, Qianyi Zhang
2004 7th International Symposium on Parallel Architectures, Algorithms and Networks, 2004. Proceedings.  
In a pipelined architecture, if a control hazard occurs, the prefetched instructions following a hazard must be discarded and removed from the pipeline before instructions from the new stream are executed  ...  Pipeline stall, branch prediction and delayed branches are techniques that have been devised to deal with this problem.  ...  is insufficient, as the operating colour of the system may be modified by more than one stage in a distributed, non-deterministic fashion.  ... 
doi:10.1109/ispan.2004.1300491 dblp:conf/ispan/TheodoropoulosZ04 fatcat:xz6v7abk4rbafp7kz4eyb2lj2e

Towards Designing Asynchronous Microprocessors: From Specification to Tape-out

Zaheer Tabassam, Syed Rameez Naqvi, Tallha Akram, Musaed Alhussein, Khursheed Aurangzeb, Sajjad Ali Haider
2019 IEEE Access  
The best case performance of NSR is estimated to be 1.3MIPS. 4) COUNTERFLOW PIPELINE PROCESSOR ARCHITECTURE Counterflow Pipeline Processor (CFPP) [67] architecture ( fig. 11 ) is realized using SPARC  ...  PROCESSOR Non-Synchronous RISC (NSR) [66] is a 16-bit load/store architecture with 16 general purpose registers and contains 5-state pipeline.  ... 
doi:10.1109/access.2019.2903126 fatcat:rwtsay62xbenhn5cgwzszhf4lm

Scaling the issue window with look-ahead latency prediction

Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Glenn Reinman
2004 Proceedings of the 18th annual international conference on Supercomputing - ICS '04  
In the commit stage, confidence counters are updated non-speculatively for the address predictor and LHT.  ...  The front end of the processor is stalled if an instruction cannot find an available queue.  ... 
doi:10.1145/1006209.1006240 dblp:conf/ics/LiuSMR04 fatcat:jsr5sz3u6vh6bbyri3spn5niiy

TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor

Yong Zhenqiang, Xiang Xiaoyan, Meng Jianyi, Chen Chen
2016 IEICE Electronics Express  
In [8], authors proposed a non-stall and dual supply voltage system which boosts local supply voltage of combinational path between erroneous stage and next stage.  ...  Generally, error correction methods include instruction replay at halved clock frequency [5] , counterflow pipelining [11], clock gating [3, 6] , and so on.  ... 
doi:10.1587/elex.13.20160766 fatcat:5hxbaxo63bg4bcqnxaysl7ftdu

The insect plane

David Jones
1999 Nature  
By speeding into stall and out again at each flap, an insect wing develops amazingly high average lift. So Daedalus is inventing a non-steadystate aircraft wing.  ...  Accelerated at a high angle of attack into the stalling regime, a wing takes a short while to stall. And until it does, it generates enormous lift.  ... 
doi:10.1038/22901 fatcat:xxkwb5pcf5fodl7u3fdbkm6zoa

Identifying and predicting timing-critical instructions to boost timing speculation

Jing Xin, Russ Joseph
2011 Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11  
Second, counterflow pipeline recovery used in Razor-like designs is sensitive to the pipeline depth of timing errors.  ...  If the instruction is flagged as critical, the scheduling logic expects a one-cycle stall during execution.  ... 
doi:10.1145/2155620.2155636 dblp:conf/micro/XinJ11 fatcat:hn5pdtpbybbqbo3b3ta7tgaoji

Error Estimation and Error Reduction with Input-Vector Profiling for Timing Speculation in Digital Circuits

Xiaowen Wang, William H. Robinson
2018 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The MOSFETs in CMOS logic normally will have some non-zero reverse leakage during RTL simulation.  ...  Instructions IF ID EX MEM stall Correct value provided to MEM MEM Razor latch gets correct EX value ST ST ST ST ST stall instruction to wri of forward progre in the correct  ... 
doi:10.1109/tcad.2018.2808240 fatcat:rfrozu53jjd5pntinkjfieklpq
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