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NoC contention analysis using a branch-and-prune algorithm

Dakshina Dasari, Borislav Nikoli'c, Vincent N'elis, Stefan M. Petters
2014 ACM Transactions on Embedded Computing Systems  
For this extended model, we propose an algorithm called "Branch and Prune" (BP). Our proposed method provides tighter and safe estimates than the existing recursive-calculus based approaches.  ...  For this extended model, we propose an algorithm called "Branch and Prune" (BP). Our proposed method provides tighter and safe estimates than the existing recursive-calculus based approaches.  ...  ACKNOWLEDGMENTS This work was partially supported by National Funds through FCT and ERDF (European Regional Development  ... 
doi:10.1145/2567937 fatcat:aankihwom5ge7bpy5mu5ctqkay

Learning-based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems [article]

Biresh Kumar Joardar, Ryan Gary Kim, Janardhan Rao Doppa, Partha Pratim Pande, Diana Marculescu, Radu Marculescu
2018 arXiv   pre-print
The rising use of deep learning and other big-data algorithms has led to an increasing demand for hardware platforms that are computationally powerful, yet energy-efficient.  ...  However, as systems use heterogeneity (e.g., a combination of CPUs, GPUs, and accelerators) to improve performance and efficiency, it becomes more pertinent to address the distinct and likely conflicting  ...  A recent work [12] proposed a branch-andbound-based algorithm, priority and compensation factororiented branch and bound (PCBB) for task mapping in a NoC-based platform [12] .  ... 
arXiv:1810.08869v1 fatcat:a3itqouqebeprgtbwk66ceh3ny

NoC-Based Hardware Accelerator for Breakpoint Phylogeny

Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman
2012 IEEE transactions on computers  
Exponential time algorithms that apply efficient runtime heuristics, such as branch-and-bound, to dynamically prune the search space are used to solve TSP.  ...  In this paper, we present the design and performance evaluation of a network-on-chip (NoC)-based implementation for solving TSP under the bounded edge-weight model, as used in the computation of breakpoint  ...  ACKNOWLEDGMENTS We thank biologists Professor Eric Roalson and Amit Dhingra for suggesting the real inputs that were used to test our NoC design.  ... 
doi:10.1109/tc.2011.100 fatcat:pvg6d4n3b5bcjgjbn6cwd4fkjy

Channel trees

Andreas Hansson, Martijn Coenen, Kees Goossens
2007 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '07  
We show how channel trees enable us to halve the latter in a car entertainment SoC, and reduce the average latency by as much as much as 52% in a mobile phone SoC.  ...  latency and TDM-table size.  ...  Soft real-time (SRT) applications, e.g. an MPEG decoder, can tolerate deadline misses with only a modest quality degradation and SRT analysis techniques are used for average-case performance analysis  ... 
doi:10.1145/1289816.1289855 dblp:conf/codes/HanssonCG07 fatcat:lkjy4cwynzgg5iz7ekm7zt74sq

Improved priority assignment for real-time communications in on-chip networks

Meng Liu, Matthias Becker, Moris Behnam, Thomas Nolte
2015 Proceedings of the 23rd International Conference on Real Time and Networks Systems - RTNS '15  
Fixed-priority based preemptive scheduling using virtual-channels is a solution to support real-time communications in on-chip networks.  ...  In this paper, we present two undirected-graph based priority assignment algorithms, the GESA and the GHSA.  ...  On the other hand, even though the HSA uses heuristic functions and a branch pruning policy to reduce the search space, the algorithm is still not very efficient.  ... 
doi:10.1145/2834848.2834867 dblp:conf/rtns/LiuBBN15 fatcat:wjhs6dzly5gjrix35p3greq3bq

Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip [chapter]

Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris Myers
2014 Lecture Notes in Computer Science  
Adding faulttolerance adaptivity to a routing algorithm increases its design complexity and makes it prone to deadlock and other problems if improperly implemented.  ...  A fault-tolerant routing algorithm in Network-on-Chip architectures provides adaptivity for on-chip communications.  ...  The contents of each flit is represented by a natural number, and the arbiter process uses the variable "one_flit" of type Nat to store the flit travelling through it.  ... 
doi:10.1007/978-3-319-10702-8_4 fatcat:naxfhztyqzb73feg5bwdr2frbe

A Survey of Machine Learning for Computer Architecture and Systems [article]

Nan Wu, Yuan Xie
2021 arXiv   pre-print
For ML-based design methodology, we follow a bottom-up path to review current work, with a scope of (micro-)architecture design (memory, branch prediction, NoC), coordination between architecture/system  ...  It has been a long time that computer architecture and systems are optimized to enable efficient execution of machine learning (ML) algorithms or models.  ...  In order to better model interactions among multiple agents, a multi-agent coordination algorithm with fuzzy RL [227] can be used to solve the dynamic content allocation in content delivery networks  ... 
arXiv:2102.07952v1 fatcat:vzj776a6abesljetqobakoc3dq

Mapping Cores on Network-on-Chip

Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
2005 International Journal of Computational Intelligence Research  
The paper addresses the problem of topological mapping of intellectual properties (IPs) on the tiles of a meshbased network on chip (NoC) architecture.  ...  At the same time, two of the most widely-known approaches to mapping in mesh-based NoC architectures are extended in order to explore the mapping space in a multi-criteria mode.  ...  Hu and Marculescu [17] present a branch and bound algorithm for mapping IPs/cores in a mesh-based NoC architecture that minimizes the total amount of power consumed in communications with the constraint  ... 
doi:10.5019/j.ijcir.2005.29 fatcat:emuz66oq2zc5nk2gahf3q72mjm

CAP Bench: a benchmark suite for performance and energy evaluation of low-power many-core processors

Matheus A. Souza, Pedro Henrique Penna, Matheus M. Queiroz, Alyson D. Pereira, Luís Fabricio Wanderley Góes, Henrique C. Freitas, Márcio Castro, Philippe O.A. Navaux, Jean-François Méhaut
2016 Concurrency and Computation  
This pruning introduces irregularities in the algorithm, since the depth-first search needs to discard branches depending on the order in which the branches are searched.  ...  The algorithm does a depth-first search looking for the shortest path, pruning paths that have a bigger cost than the current minimum cost.  ... 
doi:10.1002/cpe.3892 fatcat:p6hjcjpke5c25feqfiecv6tx7i

A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

Andreas Hansson, Kees Goossens, Andrei Rădulescu
2007 VLSI design (Print)  
Known solutions to the mapping and routing problems first map cores onto a topology and then route communication, using separate and possibly conflicting objective functions.  ...  In this paper, we present a unified single-objective algorithm, called Unified MApping, Routing, and Slot allocation (UMARS+).  ...  The solution space traversal method used to solve the QAP in [8, 18] is a restricted branch-and-bound [22] algorithm.  ... 
doi:10.1155/2007/68432 fatcat:faqmoogr6fgxni2nvpix7dg7jy

A comprehensive power-performance model for NoCs with multi-flit channel buffers

Mohammad Arjomand, Hamid Sarbazi-Azad
2009 Proceedings of the 23rd international conference on Conference on Supercomputing - ICS '09  
This necessitates an exhaustive analysis of NoCs for future designs.  ...  Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication.  ...  Although exploration of the design space in such algorithms is mostly NP-Hard, they generally utilize heuristic [13] or branch-and-bound [8] techniques to prune design space within an acceptable time  ... 
doi:10.1145/1542275.1542341 dblp:conf/ics/ArjomandS09 fatcat:kt32rdpq3naoviukjqruglcnza

Constraint-driven bus matrix synthesis for MPSoC

Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
and up to 3.2 × savings when compared to a maximally connected reduced bus matrix.  ...  In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture which satisfies all performance constraints in the design and minimizes  ...  Acknowledgements This research was partially supported by grants from SRC Contract 1330, Conexant Systems, CPCC fellowship and UC Micro (03-029).  ... 
doi:10.1145/1118299.1118309 fatcat:6e3wslf7s5e6bkiwqzde7t33wu

Toward accurate detection on change barriers

Tingting Lv, Zhilei Ren, Xiaochen Li, Guojun Gao, He Jiang
2021 Science China Information Sciences  
The experimental results show that our method achieves 81.8%-100% precision and recall, outperforming existing algorithms by 10%-30%.  ...  We analyze the characteristics of change barriers and extract domain-specific metrics to train a Logistic Regression model for detection.  ...  As a rule-based algorithm, JRip outputs a set of rules just like the decision tree algorithm. It is necessary to complete the four stages of construction, growth, pruning, and optimization.  ... 
doi:10.1007/s11432-019-2902-5 fatcat:44jjkb3gojcbrnvqjrixu5dol4

A unified approach to constrained mapping and routing on network-on-chip architectures

Andreas Hansson, Kees Goossens, Andrei Rǎdulescu
2005 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05  
Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions.  ...  In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS).  ...  In [11] a branch-and-bound algorithm is used to map cores onto a tile-based architecture, aiming to minimize energy while bandwidth constraints are satisfied.  ... 
doi:10.1145/1084834.1084857 dblp:conf/codes/HanssonGR05 fatcat:b2qif72onrho7ijdtbj7cooahu

Improving Symbolic System-Level Synthesis by Solver Coordination and Domain-Specific Heuristics

Christian Haubelt, Alexander Rausch
2022 Electronics  
binding, and a background theory solver performing schedulability analysis.  ...  For these methods, in order to prune the search space of infeasible implementations efficiently, a feedback by the background theory is required.  ...  Since this optimization strategy cannot be used together with domain-specific heuristics, we used a branch and bound optimization strategy (-opt-strategy=bb,2) when necessary.  ... 
doi:10.3390/electronics11121888 doaj:31d27f8d6a774a1fb08d76845d5f06f6 fatcat:mk5mttzyzvgszjbwr4ulewe6ve
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