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New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology

Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
This paper proposes new SOI circuit strategies for simultaneous reduction of standby gate and sub-threshold leakages. Various enhanced MTCMOS design alternatives are analyzed.  ...  A new method for assigning the V TH and sizes of header and footer transistors is proposed, and stacking of headers/footers is analyzed.  ...  detail for enhanced SOI MTCMOS techniques and has deduced optimal design points for various cases.  ... 
doi:10.1145/871546.871548 fatcat:pdcqpt3a75e5zkxsii6mxghkpm

New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology

Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
This paper proposes new SOI circuit strategies for simultaneous reduction of standby gate and sub-threshold leakages. Various enhanced MTCMOS design alternatives are analyzed.  ...  A new method for assigning the V TH and sizes of header and footer transistors is proposed, and stacking of headers/footers is analyzed.  ...  detail for enhanced SOI MTCMOS techniques and has deduced optimal design points for various cases.  ... 
doi:10.1145/871506.871548 dblp:conf/islped/DasJCCB03 fatcat:k6srser4trffnhzwm76oacrf2a

New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology

K.K. Das, R.V. Joshi, Ching-Te Chuang, P.W. Cook, R.B. Brown
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.  
This paper proposes new SOI circuit strategies for simultaneous reduction of standby gate and sub-threshold leakages. Various enhanced MTCMOS design alternatives are analyzed.  ...  A new method for assigning the V TH and sizes of header and footer transistors is proposed, and stacking of headers/footers is analyzed.  ...  detail for enhanced SOI MTCMOS techniques and has deduced optimal design points for various cases.  ... 
doi:10.1109/lpe.2003.1231855 fatcat:2skkt2h4sjdajiccxitx66itoe

Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design

Ramesh Vaddi, Rajendra P. Agarwal, Sudeb Dasgupta, Tony T. Kim
2011 Journal of Low Power Electronics and Applications  
DGMOSFETs for robust and ultra-low power subthreshold circuit design and comparison with nano-scale bulk CMOS are described in Section 3.  ...  With this view, this work focuses on DGMOSFETs for optimal ultra-low power subthreshold circuit design.  ... 
doi:10.3390/jlpea1020277 fatcat:4davlr4xm5bkhlbduy7pcdnkcu

Table of Content

2022 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)  
Technology for Chiplet Design T1-20 Study of Carrier Scattering and Mobility in Monolayer MoTe2 and WTe2 by First-Principle Analysis T1-21 Al2O3-HfO2 Mixed High-k Dielectrics for MIM Decoupling Capacitors  ...  Parameters Variations and Scaling Strategy for High Frequency Performance Enhancement in Nanoscale CMOS T1-11 High-Resistivity Substrates with PN Interface Passivation in 22 nm FD-SOI T1-12 Deep Learning  ... 
doi:10.1109/vlsi-tsa54299.2022.9770975 fatcat:tq4sdvuddreyrlcvhamd4n5izq

Challenges for Nanoscale MOSFETs and Emerging Nanoelectronics

Yong-Bin Kim
2010 Transactions on Electrical and Electronic Materials  
Therefore, new design flows and tools are needed to optimize nanoelectronic circuits for better performance and yield.  ...  Therefore, new novel fault and defect tolerance circuit design technique and methodologies have to be developed for nanoelectronic low-power, high-speed and high-density systems to make the circuit reliable  ... 
doi:10.4313/teem.2010.11.3.093 fatcat:rgsgr2remfbfhaiz4xzelisbf4

Technical Program

2021 2021 IEEE Latin America Electron Devices Conference (LAEDC)  
Operation Range Analog circuits Strategy for Simulation of Analog Circuits with GCSOI MOSFET using BSIM SOI model Analytical model Analysis of the ZTC-Point for Vertically Stacked Nanosheet pMOS  ...  and millimeter-wave performance SOI technologies for RF and millimeter-wave integrated circuits Rf cmos SOI technologies for RF and millimeter-wave integrated circuits RF measurements Influence of Calibration  ... 
doi:10.1109/laedc51812.2021.9437946 fatcat:7j6djeusvzg2jiiem7qibbqsg4

Ultra-Low-Power FDSOI Neural Circuits for Extreme-Edge Neuromorphic Intelligence [article]

Arianna Rubino, Can Livanelioglu, Ning Qiao, Melika Payvand, Giacomo Indiveri
2020 arXiv   pre-print
Specifically, we explore the options of advanced FDSOI technologies to address analog design issues and optimize the design of the synapse integrator and of the adaptive neuron circuits accordingly.  ...  We present circuit simulation results and demonstrate the circuit's ability to produce biologically plausible neural dynamics with compact designs, optimized for the realization of large-scale spiking  ...  ACKNOWLEDGMENT We are grateful to Mohammad Ali Sharif Shazileh, Manu Nair, and Elisa Donati for fruitful discussions on the manuscript and circuit design.  ... 
arXiv:2006.14270v2 fatcat:j2fg7fiagvhh3b6gthab5kz6oq

ISDCS 2021 Technical Program

2021 2021 International Symposium on Devices, Circuits and Systems (ISDCS)  
However, with the advent of low-cost technology involving new-generation materials and methods, the TFTs started finding various applications, including gas and light sensing.  ...  In the subsequent decades, many new materials and methods emerged for lowcost, room temperature fabrication of TFTs.  ...  design of ultra sensitive bio-sensors.  ... 
doi:10.1109/isdcs52006.2021.9397912 fatcat:766wjfco3fe2fgat2i42etyk5q

Microprocessors optimal power dissipation using combined threshold hopping and voltage scaling

Diary Sulaiman, Ibrahim Hamarash, Muhammed Ibrahim
2017 IEICE Electronics Express  
Dynamic threshold hopping and supply voltage scaling (DTSVS) is an effective low-power design technique for reducing dissipated power.  ...  Both theoretical and simulation results show that, optimal amount of power consumption reduction has been obtained for different temperatures and workload environments.  ...  using the body bias and pin reordering technique for nanometer-scale CMOS circuits [9] , finally, Adaptive supply and body voltage control for ultra-low power microprocessors using 22-nm technology model  ... 
doi:10.1587/elex.14.20171046 fatcat:inwwdazngbdk5olafpatmpcip4

Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices

A. Bansal, B.C. Paul, K. Roy
2005 IEEE Transactions on Electron Devices  
The absence of random doping fluctuations in undoped ultra thin body and elimination of optimization requirements on n+lp+ well isolations are plus for nano-scale FinFET based bitcell design.  ...  This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance.  ...  His research interests include low-power, robust, and high-performance circuit design for nanoscale technologies. He has many publications in journals and conferences and several patents pending.  ... 
doi:10.1109/ted.2004.842713 fatcat:ki5vlrqvczegnnbc6kuszrxzky

Enabling Always-On Sensor Nodes Entirely Powered by Sustainable Energy Sources – Making Our World Smarter and Greener

Massimo Alioto
2020 2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)  
He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IEEE-CS  ...  In this talk, we will cover the IoT design practices and core technological challenges that need to be addressed to enable widespread deployment of IoT.  ...  His primary research interests include ultra-low power circuits and systems, self-powered integrated systems, near-threshold circuits for green computing, widely energy-scalable integrated systems, circuits  ... 
doi:10.1109/ises50453.2020.00011 fatcat:gqlhvmoxivb2zlfp64umfahiji

System LSI: Challenges and Opportunities

T. KURODA
2006 IEICE transactions on electronics  
End of CMOS scaling has been discussed in many places since the late 90's. Even if the end of CMOS scaling is irrelevant, it is for sure that we are facing a turning point in semiconductor business.  ...  In this paper, challenges and opportunities of system LSI are discussed from three levels of perspectives.  ...  Yokoyama, and Prof. Kikkawa for encouragement.  ... 
doi:10.1093/ietele/e89-c.3.213 fatcat:2qtq2qcp6neqdkjlns25gjsuae

2019 Index IEEE Journal of the Electron Devices Society Vol. 7

2019 IEEE Journal of the Electron Devices Society  
., +, JEDS 2019 111-117 Optical design techniques Comprehensive Analysis and Optimal Design of Ge/GeSn/Ge p-n-p Infrared Heterojunction Phototransistors.  ...  ., +, JEDS 2019 261-267 Comprehensive Analysis and Optimal Design of Ge/GeSn/Ge p-n-p Infrared Heterojunction Phototransistors.  ... 
doi:10.1109/jeds.2020.2969758 fatcat:t5gvi7c3ofbvxfv4xv6sngquxq

Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters

Seong-Jae Cho, Shinichi O'uchi, Kazuhiko Endo, Sang-Wan Kim, Young-Hwan Son, In-Man Kang, Meishoku Masahara, James S.Jr Harris, Byung-Gook Park
2010 JSTS Journal of Semiconductor Technology and Science  
Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor  ...  In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling  ...  ACKNOWLEDGMENTS This work was supported by National Research Foundation of Korea (NRF) (previously, KOSEF) and Japan International Science and Technology Exchange Center (JISTEC).  ... 
doi:10.5573/jsts.2010.10.4.265 fatcat:puyg7uqlmbhfxgesfk5eiqvqoa
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