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On removing redundancy in sequential circuits

Kwang-Ting Cheng
1991 Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91  
For large circuits, we propose a practical procedure to identify a subset, called feedback-free sequential redundant faults, of redundant faults.  ...  Redundancies in the feedback-free circuit model are then identified and removed. This procedure could also eliminate redundant flip-flops.  ...  Acknowledgements -The interesting discussions with Vishwani Agrawal, Wu-Tung Cheng, and Kurt Keutzer on sequential circuit testing are acknowledge. The author also wish to thank Dong H.  ... 
doi:10.1145/127601.127655 dblp:conf/dac/Cheng91 fatcat:ctdcr3q3zbarlnyzaqvmpt62ma

Integrating symbolic techniques in ATPG-based sequential logic optimization

Enrique San Millán, Luis Entrena, José A. Espejo, Silvia Chiusano, Fulvio Corno
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
# This paper presents a new integrated approach to logic optimization for sequential circuits.  ...  The approach is based on the Redundancy Addition and Removal algorithm, which is based on Automatic Test Pattern Generation (ATPG) techniques, and improves it using Symbolic Techniques based on BDDs.  ...  The basic Redundancy Addition and Removal approach can be summarized as follows. A wire is selected and tested for stuck-at fault.  ... 
doi:10.1145/307418.307555 fatcat:4wlinixjdnfu5nnnhd2t4wnsei

Perturb and simplify: multilevel Boolean network optimizer

Shih-Chieh Chang, M. Marek-Sadowska, Kwang-Ting Cheng
1996 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Furthermore, we discuss the problem of adding and removing two wires, none of which alone is redundant, but when jointly added/removed they do not affect functionality of the network.  ...  In particular, we propose several new ways in which one or more redundant gates or wires can be added to a network.  ...  Redundancy identification procedure In a combinational circuit, a wire is redundant if and only if the corresponding stuck-at fault is untestable.  ... 
doi:10.1109/43.552082 fatcat:qinlp7sporbldh5kzxs2ibyghq

Postlayout logic restructuring using alternative wires

Shih-Chieh Chang, Kwang-Ting Cheng, Nam-Sung Woo, M. Marek-Sadowska
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Allowing the logic blocks to have alternative functions also increases the chance of successful routing. A redundancy addition and removal technique is used to identify such alternative wires.  ...  The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA.  ...  Fig. 3 . 3 Example of redundant wire. a wire is redundant if and only if the corresponding stuck-at fault is untestable. Fig. 5 . 5 Procedure of finding alternative wires.  ... 
doi:10.1109/43.640617 fatcat:xqtamzigozgidigzchzt7nbfzq

Design rewiring using ATPG

A. Veneris, M.S. Abadir
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
To perform this study, the authors reduce the problem of design rewiring to the process of injecting a redundant set of multiple pattern faults.  ...  This formulation arrives at a new set of results with theoretical and practical applications. Experiments demonstrate the competitiveness of the approach and motivate future work in the area.  ...  ACKNOWLEDGMENT The authors would like to thank I. Ting, M. Amiri, and R. Chang for contributions to portions of the work described here.  ... 
doi:10.1109/tcad.2002.804388 fatcat:cgy7wphp4zfb3exxsoaos7cxgy

Theorems and extensions of single wire replacement

Shih-Chieh Chang, Zhong-Zhen Wu
2001 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we discuss the theorems and extensions of single alternative wire that attempts to replace one wire by another wire without changing the logic functionality.  ...  The wire replacement technique has been successfully applied to achieve logic optimization and routability improvement.  ...  Therefore, adding wa can cause both the w t stuck-at-1 fault and stuck-at-0 fault redundant.  ... 
doi:10.1109/43.945310 fatcat:rwm5t4tjrjhnri5zuasssfpjo4

Layout driven logic synthesis for FPGAs

Shih-Chieh Chang, Kwang-Ting Cheng, Nam-Sung Woo, Malgorzata Marek-Sadowska
1994 Proceedings of the 31st annual conference on Design automation conference - DAC '94  
Allowing the logic blocks to have alternative functions also increases the flexibility of routing. The redundancy addition and removal techniques are used to identify such alternative wires.  ...  The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA.  ...  This work was supported in part by the National Science Foundation under Grant MIP 9117328 and in part by AT&T Bell Laboratories and Digital Equipment Corporation through the California MICRO program.  ... 
doi:10.1145/196244.196388 dblp:conf/dac/ChangCWM94 fatcat:h4e5brsjbjc2hiimfbfd5qarli

Circuit optimization by rewiring

Shih-Chieh Chang, L.P.P.P. Van Ginneken, M. Marek-Sadowska
1999 IEEE transactions on computers  
The optimization is based on incremental restructuring of a circuit through a sequence of additions and removals of redundant wires.  ...  During the ATPG process, certain nodes in the circuit must have particular logic assignments for a test to exist.  ...  If the MAs of a stuck-at fault test cannot be consistent, the fault is untestable and, therefore, the wire is redundant. A wire to be removed is referred to as the target wire.  ... 
doi:10.1109/12.795224 fatcat:yqbvwgt4znflzkg4kx5xdk4q6m

Testability Synthesis for Jumping Carry Adders

Chien-In Henry Chen, Mahesh Wagh
2002 VLSI design (Print)  
This paper presents a testability synthesis methodology applicable to a top–down design method based on the identification and removal of redundant faults.  ...  With the exploration of the relationship, redundancy removal can be applied to improve the testability, reduce the area and improve the speed of a synthesized circuit.  ...  remove single stuck-at fault redundancies in combinational logic circuits.  ... 
doi:10.1080/10655140290010079 fatcat:pjohywqzh5b3dcqo5j3xslh6mi

A Fast Heuristic Algorithm for Redundancy Removal [article]

Maxim Teslenko, Elena Dubrova
2015 arXiv   pre-print
Redundancy identification is an important step of the design flow that typically follows logic synthesis and optimization.  ...  In addition to reducing circuit area, power consumption, and delay, redundancy removal also improves testability.  ...  Therefore, no new redundancies would be identified. B.  ... 
arXiv:1503.06632v1 fatcat:wjmmzgxeuvdjdgy4uwe2mlef6u

Logic optimization and equivalence checking by implication analysis

W. Kunz, D. Stoffel, P.R. Menon
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG).  ...  It shows that an ordinary test generator for single stuckat faults can be used to perform arbitrary transformations in a combinational circuit and discusses how this approach relates to conventional multilevel  ...  ACKNOWLEDGMENT The authors would like to thank Mentor Graphics Inc. and in particular, A. Srinivasan for providing us with industrial designs for our experimental evaluation.  ... 
doi:10.1109/43.594832 fatcat:a76yphdbqzahxpqmvffn2f63fq

Who are the alternative wires in your neighborhood? (alternative wires identification without search)

Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
2001 Proceedings of the 11th Great Lakes Symposium on VLSI - GLSVLSI '01  
RAMBO [9] is a redundancy-addition-and-removal technique which for a given target wire w t finds a redundant alternative wire w r whose addition makes w t redundant and hence removable without changing  ...  We propose a new reasoning scheme which directly identifies alternative wires without performing any trial-and-error tests.  ...  The authors would like to thank Ric Chung-Yang Huang of Verplex Systems for providing us the RAMBAS framework [11] .  ... 
doi:10.1145/368122.368880 dblp:conf/glvlsi/ChangM01 fatcat:4ke3tug7evbwfm7qh36ugllo3u

On Synthesis-for-Testability of Combinational Logic Circuits

Irith Pomeranz
1995 Proceedings - Design Automation Conference  
Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates.  ...  We propose a synthesis method that modifies a given circuit to reduce the number of gates and the number of paths in the circuit.  ...  The results after redundancy removal are omitted if no redundant stuck-at faults were found.  ... 
doi:10.1109/dac.1995.250076 fatcat:i3h5nopufra5harbz6kunkidka

On synthesis-for-testability of combinational logic circuits

Irith Pomeranz, Sudhakar M. Reddy
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates.  ...  We propose a synthesis method that modifies a given circuit to reduce the number of gates and the number of paths in the circuit.  ...  The results after redundancy removal are omitted if no redundant stuck-at faults were found.  ... 
doi:10.1145/217474.217518 dblp:conf/dac/PomeranzR95 fatcat:gkckjbkhbzfh3ahvtdeapnfiiu

An Implicit Approach to Minimizing Range-Equivalent Circuits

Yung-Chih Chen, Chun-Yao Wang
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We then present a procedure to determine if a given range stuck-at fault on a PI is untestable.  ...  We first introduce a new concept of a stuck-at fault test for a circuit's range, showing that a range untestable stuck-at fault on a primary input (PI) indicates that this PI is range redundant, i.e.,  ...  its stuck-at 1 fault is range untestable, and hence, we do not set stuck-at 0 fault on it (we check stuck-at 1 fault first in Although the order of removed PIs affects the simplified result of the cu  ... 
doi:10.1109/tcad.2008.2006088 fatcat:j4x6hbeolbeg7fckoekvefajay
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